PIC18F6680-I/L Microchip Technology, PIC18F6680-I/L Datasheet - Page 144
PIC18F6680-I/L
Manufacturer Part Number
PIC18F6680-I/L
Description
Microcontrollers (MCU) 64KB 3328 RAM 52 I/O
Manufacturer
Microchip Technology
Datasheet
1.PCM18XK1.pdf
(496 pages)
Specifications of PIC18F6680-I/L
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.25 KB
Interface Type
I2C/SPI/AUSART/CAN
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
53
Number Of Timers
5
Operating Supply Voltage
4.2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
12-ch x 10-bit
Program Memory Type
Flash
Program Memory Size
64 KB
Package / Case
PLCC-68
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Quantity
Price
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Part Number:
PIC18F6680-I/L
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RUBYCON
Quantity:
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Part Number:
PIC18F6680-I/L
Manufacturer:
MICROCH
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PIC18F6585/8585/6680/8680
10.7
PORTG is a 6-bit wide port with 5 bidirectional pins and
1 unidirectional pin. The corresponding data direction
register is TRISG. Setting a TRISG bit (= 1) will make
the corresponding PORTG pin an input (i.e., put the
corresponding output driver in a high-impedance
mode). Clearing a TRISG bit (= 0) will make the corre-
sponding PORTG pin an output (i.e., put the contents
of the output latch on the selected pin).
The Data Latch register (LATG) is also memory mapped.
Read-modify-write operations on the LATG register read
and write the latched output value for PORTG.
Pins RG0-RG2 on PORTG are multiplexed with the CAN
peripheral. Refer to Section 23.0 “ECAN Module” for
proper settings of TRISG when CAN is enabled. RG5 is
multiplexed with MCLR/V
more information.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTG pin. Some
peripherals override the TRIS bit to make a pin an output,
while other peripherals override the TRIS bit to make a
pin an input. The user should refer to the corresponding
peripheral section for the correct TRIS bit settings.
FIGURE 10-16:
DS30491C-page 142
Note:
Note: I/O pins have diode protection to V
Data Bus
WR PORTG or
WR LATG
WR TRISG
RD TRISG
RD PORTG
TXD
PORTG, TRISG and LATG
Registers
On a Power-on Reset, these pins are
configured as digital inputs.
RG0/CANTX1 PIN BLOCK DIAGRAM
PP
. Refer to Register 24-5 for
TRIS Latch
Data Latch
RD LATG
D
D
CK
CK
Q
Q
Q
Q
DD
and V
SS
0
1
OPMODE2:OPMODE0 = 000
.
The pin override value is not loaded into the TRIS reg-
ister. This allows read-modify-write of the TRIS register
without concern due to peripheral overrides.
EXAMPLE 10-7:
CLRF
CLRF
MOVLW 04h
MOVWF TRISG
Note 1: On a Power-on Reset, RG5 is enabled as
Q
EN
2: If the device Master Clear is disabled,
PORTG
LATG
EN
D
a digital input only if Master Clear
functionality is disabled (MCLRE = 0).
verify that either of the following is done to
ensure proper entry into ICSP mode:
a) disable Low-Voltage Programming
b) make certain that RB5/KBI1/PGM is
(CONFIG4L<2> = 0); or
held low during entry into ICSP.
V
V
P
N
DD
SS
; Initialize PORTG by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RG1:RG0 as outputs
; RG2 as input
; RG4:RG3 as inputs
ENDRHI
INITIALIZING PORT
OPMODE2:OPMODE0 = 000
2004 Microchip Technology Inc.
Schmitt
Trigger
I/O pin
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