MPC8536BVTATH Freescale Semiconductor, MPC8536BVTATH Datasheet - Page 53

• Manufacturer Part Number: MPC8536BVTATH
• Description: Microprocessors (MPU) 8536 INDUSTRIAL 1250
• Manufacturer: Freescale Semiconductor

Specifications of MPC8536BVTATH

• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 1250 MHz
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: 0 C
• Package / Case: FCPBGA-783
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

At recommended operating conditions with L/TV
Fall time TSECn_RX_CLK (80%–20%)
RXD[1:0], CRS_DV, RX_ER setup time to TSECn_RX_CLK rising edge
RXD[1:0], CRS_DV, RX_ER hold time to TSECn_RX_CLK rising edge
Note:
1. The symbols used for timing specifications herein follow the pattern of t
Figure 27
Figure 28
2.9.3
Each SGMII port features a 4-wire AC-Coupled serial link from the dedicated SerDes 2 interface of MPC8535E as shown in
Figure
pair features 50-Ω output impedance. Each input of the SerDes receiver differential pair features 50-Ω on-die termination to
S2GND (xcorevss). The reference circuit of the SerDes transmitter and receiver is shown in
When an eTSEC port is configured to operate in SGMII mode, the parallel interface’s output signals of this eTSEC port can be
left floating. The input signals should be terminated based on the guidelines described in
Recommendations,”
applicable.
Freescale Semiconductor
for inputs and t
timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t
to the high (H) state or setup time. Also, t
(D) went invalid (X) relative to the t
reference symbol representation is based on three letters representing the clock of a particular functional. For example, the
subscript of t
appropriate letter: R (rise) or F (fall).
29, where C
provides the AC test load for eTSEC.
shows the RMII receive AC timing diagram.
SGMII Interface Electrical Characteristics
MRX
TSECn_RX_CLK
(first two letters of functional block)(reference)(state)(signal)(state)
TX
represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3
as long as such termination does not violate the desired POR configuration requirement on these pins, if
is the external (on board) AC-Coupled capacitor. Each output pin of the SerDes transmitter differential
RXD[1:0]
CRS_DV
Parameter/Condition
RX_ER
Table 37. RMII Receive AC Timing Specifications (continued)
Output
MRX
Figure 28. RMII Receive AC Timing Diagram
clock reference (K) going to the low (L) state or hold time. Note that, in general, the clock
DD
MRDXKL
t
RMRH
Figure 27. eTSEC AC Test Load
of 3.3 V ± 5%.
t
RMRDV
Z
0
symbolizes MII receive timing (GR) with respect to the time data input signals
t
= 50 Ω
RMR
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
Valid Data
t
for outputs. For example, t
RMRF
(first two letters of functional block)(signal)(state) (reference)(state)
Symbol
t
t
RMRDX
t
RMRDV
R
RMRF
L
= 50 Ω
t
RMRDX
t
1
RMRR
Min
1.0
4.0
2.0
Section 3.6, “Connection
LV
Figure
DD
MRDVKH
/2
MRX
Typ
68.
—
—
—
clock reference (K) going
symbolizes MII receive
Max
2.0
—
—
Unit
ns
ns
ns
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