MPC8536BVTATH Freescale Semiconductor, MPC8536BVTATH Datasheet - Page 67

• Manufacturer Part Number: MPC8536BVTATH
• Description: Microprocessors (MPU) 8536 INDUSTRIAL 1250
• Manufacturer: Freescale Semiconductor

Specifications of MPC8536BVTATH

• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 1250 MHz
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: 0 C
• Package / Case: FCPBGA-783
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Local bus cycle time
Local bus duty cycle
LCLK[n] skew to LCLK[m] or LSYNC_OUT
Input setup to local bus clock (except LUPWAIT)
LUPWAIT input setup to local bus clock
Input hold from local bus clock (except LUPWAIT)
LUPWAIT input hold from local bus clock
LALE output transition to LAD/LDP output transition (LATCH
setup and hold time)
Local bus clock to output valid (except LAD/LDP and LALE)
Local bus clock to data valid for LAD/LDP
Local bus clock to address valid for LAD
Local bus clock to LALE assertion
Output hold from local bus clock (except LAD/LDP and LALE)
Output hold from local bus clock for LAD/LDP
Local bus clock to output high Impedance (except LAD/LDP and LALE)
Local bus clock to output high impedance for LAD/LDP
Note:
1. The symbols used for timing specifications herein follow the pattern of t
2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode.
3. All signals are measured from BV
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through
6.t
7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
Table 52
Freescale Semiconductor
for inputs and t
timing (LB) for the input (I) to go invalid (X) with respect to the time the t
clock one(1). Also, t
output (O) going invalid (X) or output hold time.
bypass mode to 0.4 × BV
the component pin is less than or equal to the leakage current specification.
LBOTOT
with LBCR[AHD] = 0.
complementary signals at BV
describes the general timing parameters of the local bus interface at BV
is a measurement of the minimum time between the negation of LALE and any change in LAD. t
Table 51. Local Bus General Timing Parameters (BV
(First two letters of functional block)(reference)(state)(signal)(state)
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3
LBKHOX
Table 52. Local Bus General Timing Parameters (BV
Parameter
DD
symbolizes local bus timing (LB) for the t
of the signal in question for 3.3-V signaling levels.
DD
/2.
Parameter
DD
/2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock for PLL
Configuration Symbol
—
—
—
—
—
—
—
—
—
—
—
—
—
LBK
for outputs. For example, t
(First two letters of functional block)(signal)(state) (reference)(state)
LBK
clock reference (K) to go high (H), with respect to the
clock reference (K) goes high (H), in this case for
t
t
LBKH/
t
t
t
t
t
DD
t
t
t
t
LBKSKEW
t
LBKHOV1
LBKHOV2
LBKHOV3
LBKHOV4
LBKHOX1
LBIVKH1
LBIVKH2
LBIXKH1
LBIXKH2
LBOTOT
t
DD
LBK
= 3.3 V DC) (continued)
Symbol
t
t
t
t
LBK
LBKHOX2
LBKHOZ1
LBKHOZ2
= 2.5 V DC.
enhanced Local Bus Controller (eLBC)
DD
1
= 2.5 V DC)
Min
7.5
1.9
1.8
1.1
1.1
1.5
0.8
1
43
—
—
—
—
—
Min
0.7
LBIXKH1
—
—
Max
150
2.4
2.5
2.4
2.4
12
57
—
—
—
—
—
—
Max
LBOTOT
2.5
2.5
symbolizes local bus
—
Unit
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
is guaranteed
Unit
ns
ns
ns
Notes
Notes
3, 4
3, 4
3, 4
3, 4
—
—
2
7
6
3
3
3
3
3
5
5
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