MPC8536BVTATH Freescale Semiconductor, MPC8536BVTATH Datasheet - Page 72

• Manufacturer Part Number: MPC8536BVTATH
• Description: Microprocessors (MPU) 8536 INDUSTRIAL 1250
• Manufacturer: Freescale Semiconductor

Specifications of MPC8536BVTATH

• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 1250 MHz
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: 0 C
• Package / Case: FCPBGA-783
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

enhanced Local Bus Controller (eLBC)
Local bus clock to data valid for LAD/LDP
Local bus clock to address valid for LAD, and LALE
Local bus clock to LALE assertion
Output hold from local bus clock (except LAD/LDP and LALE)
Output hold from local bus clock for LAD/LDP
Local bus clock to output high Impedance (except LAD/LDP and LALE)
Local bus clock to output high impedance for LAD/LDP
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
2. All timings are in reference to local bus clock for PLL bypass mode.
3. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
4. All signals are measured from BVDD/2 of the rising edge of local bus clock for PLL bypass mode to 0.4 x BVDD of the signal
5. Input timings are measured at the pin.
6. t
7. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through
8. These timing parameters for PLL bypass mode are defined in the opposite direction of the PLL enabled output hold timing
72
LBOTOT
for inputs and t
timing (LB) for the input (I) to go invalid (X) with respect to the time the t
clock one(1). Also, t
output (O) going invalid (X) or output hold time.
complementary signals at BV
in question for 3.3-V signaling levels.
with LBCR[AHD] = 0.
the component pin is less than or equal to the leakage current specification.
parameters.
is a measurement of the minimum time between the negation of LALE and any change in LAD. t
Table 54. Local Bus General Timing Parameters—PLL Bypassed (continued)
(First two letters of functional block)(reference)(state)(signal)(state)
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3
LBKHOX
symbolizes local bus timing (LB) for the t
DD
Parameter
/2.
LBK
for outputs. For example, t
(First two letters of functional block)(signal)(state) (reference)(state)
LBK
clock reference (K) to go high (H), with respect to the
clock reference (K) goes high (H), in this case for
Symbol
t
t
t
t
t
t
t
LBKLOV2
LBKLOV3
LBKLOV4
LBKLOX1
LBKLOX2
LBKLOZ1
LBKLOZ2
1
Min
—
—
—
—
—
—
—
LBIXKH1
Freescale Semiconductor
Max
0.5
0.5
0.5
2.2
2.2
0.1
0.1
LBOTOT
symbolizes local bus
Unit
is guaranteed
ns
ns
ns
ns
ns
ns
ns
Notes
4,8
4,8
4
4
4
7
7