A2F500M3G-FGG484 Actel, A2F500M3G-FGG484 Datasheet - Page 101

FPGA - Field Programmable Gate Array 500K System Gates

A2F500M3G-FGG484

Manufacturer Part Number
A2F500M3G-FGG484
Description
FPGA - Field Programmable Gate Array 500K System Gates
Manufacturer
Actel
Datasheet

Specifications of A2F500M3G-FGG484

Processor Series
A2F500
Core
ARM Cortex M3
Number Of Logic Blocks
24
Maximum Operating Frequency
100 MHz
Number Of Programmable I/os
204
Data Ram Size
64 KB
Delay Time
50 ns
Supply Voltage (max)
3.6 V
Supply Current
2 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
1.5 V
Number Of Gates
500000
Package / Case
FPBGA-484
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
A2F500M3G-FGG484
Manufacturer:
ACTEL
Quantity:
6 800
Part Number:
A2F500M3G-FGG484
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
A2F500M3G-FGG484
Quantity:
140
Part Number:
A2F500M3G-FGG484I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
A2F500M3G-FGG484I
Manufacturer:
ACTEL/爱特
Quantity:
20 000
Table 2-99 • I
Figure 2-47 • I2C Timing Parameter Definition
SDA
SCL
Parameter
t
t
Notes:
1. These maximum values are provided for information only. Minimum output buffer resistance values depend on
2. These values are provided for a load of 100 pF and 400 pF. For board design considerations and detailed output buffer
3. For allowable Pclk configurations, refer to the Inter-Integrated Circuit (I
SU;STO
FILT
VCCxxxxIOBx, drive strength selection, temperature, and process. For board design considerations and detailed output
buffer resistances, use the corresponding IBIS models located on the SoC Products Group website at
http://www.actel.com/download/ibis/default.aspx.
resistances,
http://www.actel.com/download/ibis/default.aspx.
Microcontroller Subsystem User’s
t
SU;STA
Commercial Case Conditions: T
STOP setup time
Maximum spike width filtered
2
C Characteristics
S
use
t
HD;STA
the
Definition
t
LOW
T
RISE
corresponding
3
t
Guide.
HIGH
t
HD;DAT
T
FALL
IBIS
J
= 85ºC, V
models
t
SU;DAT
DD
R e v i s i o n 6
Condition
located
= 1.425 V, –1 Speed Grade (continued)
on
SmartFusion Intelligent Mixed Signal FPGAs
2
the
C) Peripherals section in the
SoC
Products
Value
50
1
Group
t
SU;STO
P
SmartFusion
website
pclk cycles
Unit
ns
2- 89
at

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