A2F500M3G-FGG484 Actel, A2F500M3G-FGG484 Datasheet - Page 20

• Manufacturer Part Number: A2F500M3G-FGG484
• Description: FPGA - Field Programmable Gate Array 500K System Gates
• Manufacturer: Actel

Specifications of A2F500M3G-FGG484

• Processor Series: A2F500
• Core: ARM Cortex M3
• Number Of Logic Blocks: 24
• Maximum Operating Frequency: 100 MHz
• Number Of Programmable I/os: 204
• Data Ram Size: 64 KB
• Delay Time: 50 ns
• Supply Voltage (max): 3.6 V
• Supply Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.5 V
• Number Of Gates: 500000
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SmartFusion DC and Switching Characteristics
2 - 8
Theta-JA
Junction-to-ambient thermal resistance (θ
JEDEC (JESD-51), but it has little relevance in actual performance of the product. It should be used with
caution but is useful for comparing the thermal performance of one package to another.
A sample calculation showing the maximum power dissipation allowed for the A2F200-FG484 package
under forced convection of 1.0 m/s and 75°C ambient temperature is as follows:
where
The power consumption of a device can be calculated using the Microsemi SoC Products Group power
calculator. The device's power consumption must be lower than the calculated maximum power
dissipation by the package. If the power consumption is higher than the device's maximum allowable
power dissipation, a heat sink can be attached on top of the case, or the airflow inside the system must
be increased.
Theta-JB
Junction-to-board thermal resistance (θ
surface of the chip to the PCB. As defined by the JEDEC (JESD-51) standard, the thermal resistance
from junction to board uses an isothermal ring cold plate zone concept. The ring cold plate is simply a
means to generate an isothermal boundary condition at the perimeter. The cold plate is mounted on a
JEDEC standard board with a minimum distance of 5.0 mm away from the package edge.
Theta-JC
Junction-to-case thermal resistance (θ
surface of the chip to the top or bottom surface of the package. It is applicable for packages used with
external heat sinks. Constant temperature is applied to the surface in consideration and acts as a
boundary condition. This only applies to situations where all or nearly all of the heat is dissipated through
the surface in consideration.
Calculation for Heat Sink
For example, in a design implemented in an A2F200-FG484 package with 2.5 m/s airflow, the power
consumption value using the power calculator is 3.00 W. The user-dependent T
follows:
From the datasheet:
θ
T
T
T
θ
θ
JA
JA
JC
A
A
J
=
=
= 19.00°C/W (taken from
= 75.00°C
=
=
100.00°C
70.00°C
17.00°C/W
8.28°C/W
Maximum Power Allowed
Maximum Power Allowed
Table 2-6 on page
JB
JC
) measures the ability of the package to dissipate heat from the
) measures the ability of a device to dissipate heat from the
JA
R e vi s i o n 6
) is determined under standard conditions specified by
=
100.00°C 75.00°C
----------------------------------------------------
2-7).
=
19.00°C/W
T
-------------------------------------------- -
J(MAX)
–
θ
–
JA
T
A(MAX)
=
1.3 W
a
and T
j
are given as
EQ 4
EQ 5