A2F500M3G-FGG484 Actel, A2F500M3G-FGG484 Datasheet - Page 113

• Manufacturer Part Number: A2F500M3G-FGG484
• Description: FPGA - Field Programmable Gate Array 500K System Gates
• Manufacturer: Actel

Specifications of A2F500M3G-FGG484

• Processor Series: A2F500
• Core: ARM Cortex M3
• Number Of Logic Blocks: 24
• Maximum Operating Frequency: 100 MHz
• Number Of Programmable I/os: 204
• Data Ram Size: 64 KB
• Delay Time: 50 ns
• Supply Voltage (max): 3.6 V
• Supply Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.5 V
• Number Of Gates: 500000
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Name
VCCMAINXTAL
VCCMSSIOB2
VCCMSSIOB4
VCCPLLx
VCCRCOSC
VCOMPLAx
VDDBAT
VJTAG
VPP
Notes:
1. The following 3.3 V supplies should be connected together while following proper noise filtering practices: VCC33A,
2. The following 1.5 V supplies should be connected together while following proper noise filtering practices: VCC,
VCC33ADCx, VCC33AP, VCC33SDDx, VCCMAINXTAL, and VCCLPXTAL.
VCC15A, and VCC15ADCx.
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Type
Analog supply to the main crystal oscillator circuit
Supply voltage to the microcontroller subsystem I/O bank 2 (east MSS I/O bank) for the
output buffers and I/O logic
Supply voltage to the microcontroller subsystem I/O bank 4 (west MSS I/O bank) for the
output buffers and I/O logic.
Each bank can have a separate VCCMSSIO connection. All I/Os in a bank will run off
the same VCCMSSIO supply. VCCMSSIO can be 1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal
voltage. Unused I/O banks should have their corresponding VCCMSSIO pins tied to
GND.
Each bank can have a separate VCCMSSIO connection. All I/Os in a bank will run off
the same VCCMSSIO supply. VCCMSSIO can be 1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal
voltage. Unused I/O banks should have their corresponding VCCMSSIO pins tied to
GND.
Analog 1.5 V supply to the PLL
Analog supply to the integrated RC oscillator circuit
Analog ground for the PLL
External battery connection to the low power 32 KHz crystal oscillator (along with
VCCLPXTAL), RTC, and battery switchover circuit
Digital supply to the JTAG controller
SmartFusion devices have a separate bank for the dedicated JTAG pins. The JTAG
pins can be run at any voltage from 1.5 V to 3.3 V (nominal). Isolating the JTAG power
supply in a separate I/O bank gives greater flexibility in supply selection and simplifies
power supply and PCB design. If the JTAG interface is neither used nor planned to be
used, the V
is required to be powered for JTAG operation; VJTAG alone is insufficient. If a
SmartFusion device is in a JTAG chain of interconnected boards and it is desired to
power down the board containing the device, this can be done provided both VJTAG
and VCC to the device remain powered; otherwise, JTAG signals will not be able to
transition the device, even in bypass mode. See
Digital programming circuitry supply
SmartFusion devices support single-voltage in-system programming (ISP) of the
configuration flash, embedded FlashROM (eFROM), and embedded nonvolatile
memory (eNVM).
For programming, VPP should be in the 3.3 V ± 5% range. During normal device
operation, VPP can be left floating or can be tied to any voltage between 0 V and 3.6 V.
When the VPP pin is tied to ground, it shuts off the charge pump circuitry, resulting in no
sources of oscillation from the charge pump circuitry. For proper programming, 0.01 µF
and 0.33 µF capacitors (both rated at 16 V) are to be connected in parallel across VPP
and GND, and positioned as close to the FPGA pins as possible.
JTAG
pin together with the TRSTB pin could be tied to GND. Note that VCC
R e v i s i o n 6
Description
SmartFusion Intelligent Mixed Signal FPGAs
"JTAG Pins" section on page
5-8.
5 -3