A2F500M3G-FGG484 Actel, A2F500M3G-FGG484 Datasheet - Page 120

• Manufacturer Part Number: A2F500M3G-FGG484
• Description: FPGA - Field Programmable Gate Array 500K System Gates
• Manufacturer: Actel

Specifications of A2F500M3G-FGG484

• Processor Series: A2F500
• Core: ARM Cortex M3
• Number Of Logic Blocks: 24
• Maximum Operating Frequency: 100 MHz
• Number Of Programmable I/os: 204
• Data Ram Size: 64 KB
• Delay Time: 50 ns
• Supply Voltage (max): 3.6 V
• Supply Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.5 V
• Number Of Gates: 500000
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Descriptions
Microcontroller Subsystem (MSS)
5- 10
Name
External Memory Controller
EMC_ABx
EMC_BYTENx
EMC_CLK
EMC_CSx_N
EMC_DBx
EMC_OENx_N
EMC_RW_N
Inter-Integrated Circuit (I
I2C_0_SCL
I2C_0_SDA
I2C_1_SCL
I2C_1_SDA
Serial Peripheral Interface (SPI) Controllers
SPI_0_CLK
SPI_0_DI
SPI_0_DO
SPI_0_SS
SPI_1_CLK
SPI_1_DI
In/out
In/out
In/out
In/out
In/out
Type
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
In
In
2
C) Peripherals
Bus Size
Polarity/
LOW/2
LOW/2
LOW/2
Level
Rise
26
16
1
1
1
1
1
1
1
1
1
1
External memory controller address bus
Can also be used as an FPGA user I/O (see
External memory controller byte enable
Can also be used as an FPGA user I/O (see
External memory controller clock
Can also be used as an FPGA user I/O (see
External memory controller chip selects
Can also be used as an FPGA User IO (see
External memory controller data bus
Can also be used as an FPGA user I/O (see
External memory controller output enables
Can also be used as an FPGA User IO (see
External memory controller read/write. Read = High, write = Low.
Can also be used as an FPGA user I/O (see
I
Can also be used as an MSS GPIO (see
I
Can also be used as an MSS GPIO (see
I
Can also be used as an MSS GPIO (see
I
Can also be used as an MSS GPIO (see
Clock. First SPI.
Can also be used as an MSS GPIO (see
Data input. First SPI.
Can also be used as an MSS GPIO (see
Data output. First SPI.
Can also be used as an MSS GPIO (see
Slave select (chip select). First SPI.
Can also be used as an MSS GPIO (see
Clock. Second SPI.
Can also be used as an MSS GPIO (see
Data input. Second SPI.
Can also be used as an MSS GPIO (see
2
2
2
2
C bus serial clock output. First I
C bus serial data input/output. First I
C bus serial clock output. Second I
C bus serial data input/output. Second I
R e visio n 6
Description
2
C.
2
C.
2
C.
2
"GPIO_x" on page
"GPIO_x" on page
"GPIO_x" on page
"GPIO_x" on page
"GPIO_x" on page
"GPIO_x" on page
"GPIO_x" on page
"GPIO_x" on page
"GPIO_x" on page
"GPIO_x" on page
C.
"IO" on page
"IO" on page
"IO" on page
"IO" on page
"IO" on page
"IO" on page
"IO" on page
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