AFS600-PQG208 Actel, AFS600-PQG208 Datasheet - Page 18

• Manufacturer Part Number: AFS600-PQG208
• Description: FPGA - Field Programmable Gate Array 600K System Gates
• Manufacturer: Actel

Specifications of AFS600-PQG208

• Processor Series: AFS600
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 95
• Data Ram Size: 110592
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 600 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Device Architecture
Core Architecture
2 - 2
The system application, Level 3, is the larger user application that utilizes one or more applets.
Designing at the highest level of abstraction supported by the Actel Fusion technology stack, the
application can be easily created in FPGA gates by importing and configuring multiple applets.
In fact, in some cases an entire FPGA system design can be created without any HDL coding.
An optional MCU enables a combination of software and HDL-based design methodologies. The MCU
can be on-chip or off-chip as system requirements dictate. System portioning is very flexible, allowing the
MCU to reside above the applets or to absorb applets, or applets and backbone, if desired.
The Actel Fusion technology stack enables a very flexible design environment. Users can engage in
design across a continuum of abstraction from very low to very high.
VersaTile
Based upon successful Actel ProASIC3/E logic architecture, Fusion devices provide granularity comparable
to gate arrays. The Fusion device core consists of a sea-of-VersaTiles architecture.
As illustrated in
configured using the appropriate flash switch connections:
VersaTiles can flexibly map the logic and sequential gates of a design. The inputs of the VersaTile can
be inverted (allowing bubble pushing), and the output of the tile can connect to high-speed, very-long-line
routing resources. VersaTiles and larger functions are connected with any of the four levels of routing
hierarchy.
When the VersaTile is used as an enable D-flip-flop, the SET/CLR signal is supported by a fourth input,
which can only be routed to the core cell over the VersaNet (global) network.
The output of the VersaTile is F2 when the connection is to the ultra-fast local lines, or YL when the
connection is to the efficient long-line or very-long-line resources
Note:
Figure 2-2 • Fusion Core VersaTile
•
•
•
•
Any 3-input logic function
Latch with clear or set
D-flip-flop with clear or set
Enable D-flip-flop with clear or set (on a 4th input)
*This input can only be connected to the global clock distribution network.
Legend:
Figure
Enable
CLK
CLR
XC*
X2
CLR/
Data
X1
X3
2-2, there are four inputs in a logic VersaTile cell, and each VersaTile can be
Via (hard connection)
0
1
R e vi s i o n 1
0
1
Switch (flash connection)
(Figure
0
1
2-2).
0
1
Ground
Pin 1
Y
F2
YL