AFS600-PQG208 Actel, AFS600-PQG208 Datasheet - Page 243

• Manufacturer Part Number: AFS600-PQG208
• Description: FPGA - Field Programmable Gate Array 600K System Gates
• Manufacturer: Actel

Specifications of AFS600-PQG208

• Processor Series: AFS600
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 95
• Data Ram Size: 110592
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 600 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2. The ADC is functional with an external reference down to 1V, however to meet the performance parameters highlighted in the
datasheet refer to the VAREF specification in
VAREF
The Fusion device can be configured to generate a 2.56 V internal reference voltage that can be used by
the ADC. While using the internal reference, the reference voltage is output on the VAREF pin for use as
a system reference. If a different reference voltage is required, it can be supplied by an external source
and applied to this pin. The valid range of values that can be supplied to the ADC is 1.0 V to 3.3 V. When
VAREF is internally generated by the Fusion device, a bypass capacitor must be connected from this pin
to ground. The value of the bypass capacitor should be between 3.3 µF and 22 µF, which is based on the
needs of the individual designs. The choice of the capacitor value has an impact on the settling time it
takes the VAREF signal to reach the required specification of 2.56 V to initiate valid conversions by the
ADC. If the lower capacitor value is chosen, the settling time required for VAREF to achieve 2.56 V will
be shorter than when selecting the larger capacitor value. The above range of capacitor values supports
the accuracy specification of the ADC, which is detailed in the datasheet. Designers choosing the smaller
capacitor value will not obtain as much margin in the accuracy as that achieved with a larger capacitor
value. Depending on the capacitor value selected in the Analog System Builder, a tool in Libero IDE, an
automatic delay circuit will be generated using logic tiles available within the FPGA to ensure that
VAREF has achieved the 2.56 V value. Actel recommends customers use 10 µF as the value of the
bypass capacitor. Designers choosing to use an external VAREF need to ensure that a stable and clean
VAREF source is supplied to the VAREF pin before initiating conversions by the ADC. Designers should
also make sure that the ADCRESET signal is deasserted before initiating valid conversions.
User Pins
I/O
The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal levels are
compatible with the I/O standard selected. Unused I/O pins are configured as inputs with pull-up
resistors.
During programming, I/Os become tristated and weakly pulled up to VCCI. With the VCCI and VCC
supplies continuously powered up, when the device transitions from programming to operating mode, the
I/Os get instantly configured to the desired user configuration.
Axy
Analog I/O pin, where x is the analog pad type (C = current pad, G = Gate driver pad, T = Temperature
pad, V = Voltage pad) and y is the Analog Quad number (0 to 9). There is a minimum 1 MΩ to ground on
AV, AC, and AT. This pin can be left floating when it is unused.
ATRTNx
AT returns are the returns for the temperature sensors. The cathode terminal of the external diodes
should be connected to these pins. There is one analog return pin for every two Analog Quads. The x in
the ATRTNx designator indicates the quad pairing (x = 0 for AQ1 and AQ2, x = 1 for AQ2 and AQ3, ...,
x = 4 for AQ8 and AQ9). The signals that drive these pins are called out as ATRETURNxy in the software
(where x and y refer to the quads that share the return signal). ATRTN is internally connected to ground.
It can be left floating when it is unused. The maximum capacitance allowed across the AT pins is 500 pF.
GL
GL I/Os have access to certain clock conditioning circuitry (and the PLL) and/or have direct access to the
global network (spines). Additionally, the global I/Os can be used as Pro I/Os since they have identical
capabilities. Unused GL pins are configured as inputs with pull-up resistors. See more detailed
descriptions of global I/O connectivity in the
Refer to the
pins.
"User I/O Naming Convention" section on page 2-160
Analog Reference Voltage
User Input/Output
Analog Input/Output
Temperature Monitor Return
Globals
Table 3-2 on page
"Clock Conditioning Circuits" section on page
R e v i s i o n 1
3-3.
Actel Fusion Family of Mixed Signal FPGAs
for a description of naming of global
2-23.
2
2- 227