AFS600-PQG208 Actel, AFS600-PQG208 Datasheet - Page 98

• Manufacturer Part Number: AFS600-PQG208
• Description: FPGA - Field Programmable Gate Array 600K System Gates
• Manufacturer: Actel

Specifications of AFS600-PQG208

• Processor Series: AFS600
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 95
• Data Ram Size: 110592
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 600 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Device Architecture
Table 2-36 • Analog Block Pin Description
2- 82
Signal Name
VAREF
GNDREF
MODE[3:0]
SYSCLK
TVC[7:0]
STC[7:0]
ADCSTART
PWRDWN
ADCRESET
BUSY
CALIBRATE
DATAVALID
RESULT[11:0]
TMSTBINT
SAMPLE
VAREFSEL
CHNUMBER[4:0]
ACMCLK
ACMWEN
ACMRESET
ACMWDATA[7:0]
ACMRDATA[7:0]
ACMADDR[7:0]
CMSTB0 to CMSTB9
Table 2-36
explained in detail in the following sections.
describes each pin in the Analog Block. Each function within the Analog Block will be
Number
of Bits
12
10
1
1
4
1
8
8
1
1
1
1
1
1
1
1
1
5
1
1
1
8
8
8
Input/Output Voltage reference for ADC
Direction
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
R e visio n 1
External ground reference
ADC operating mode
External system clock
Clock divide control
Sample time control
Start of conversion
ADC comparator power-down if 1.
When asserted, the ADC will stop
functioning, and the digital portion of
the
operating.
status flags from the analog block.
Therefore, Actel does not recommend
asserting the PWRDWN pin.
ADC resets and disables Analog Quad
– active high
1 – Running conversion
1 – Power-up calibration
1 – Valid conversion result
Conversion result
Internal temp. monitor strobe
1 – An analog signal is actively being
sampled (stays high during signal
acquisition only)
0 – No analog signal is being sampled
0 = Output internal voltage reference
(2.56 V) to VAREF
1 = Input external voltage reference
from VAREF and GNDREF
Analog input channel select
ACM clock
ACM write enable – active high
ACM reset – active low
ACM write data
ACM read data
ACM address
Current monitor strobe – 1 per quad,
active high
analog
This may result in invalid
Function
block
will
continue
Analog Quad
Location of
multiplexer
Details
Input
ACM
ACM
ACM
ACM
ACM
ACM
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC