AFS600-PQG208 Actel, AFS600-PQG208 Datasheet - Page 279

• Manufacturer Part Number: AFS600-PQG208
• Description: FPGA - Field Programmable Gate Array 600K System Gates
• Manufacturer: Actel

Specifications of AFS600-PQG208

• Processor Series: AFS600
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 95
• Data Ram Size: 110592
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 600 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I/O Input and Output Buffer Contribution—P
This example uses LVTTL 3.3 V I/O cells. The output buffers are 12 mA–capable, configured with high
output slew and driving a 35 pF output load.
RAM Contribution—P
P
P
P
P
Operating Mode
P
P
P
P
P
P
P
P
P
Standby Mode and Sleep Mode
P
P
P
Operating Mode
P
P
P
Standby Mode and Sleep Mode
P
S-CELL
C-CELL
NET
LOGIC
INPUTS
INPUTS
INPUTS
OUTPUTS
OUTPUTS
I/O
I/O
INPUTS
I/O
MEMORY
MEMORY
MEMORY
MEMORY
OUTPUTS
I/O
OUTPUTS
F
Number of input pins used: N
Number of output pins used: N
Estimated I/O buffer toggle rate:
Estimated IO buffer enable rate:
Frequency of Read Clock: F
Frequency of Write Clock: F
Number of RAM blocks: N
Estimated RAM Read Enable Rate:
Estimated RAM Write Enable Rate:
= P
= 1.30 mW + 47.47 mW
= 0 W
= 48.77 mW
CLK
= 0 W
= 0 W
INPUTS
= 0 W
= 0 W
= N
= 30 * (0.1 / 2) * 0.01739 * 50
= 1.30 mW
= 0 W
= 50 MHz
= (N
= (20 * 0.025 * 0.125 * 10) + (20 * 0.030 * 0.125 * 10)
= 1.38 mW
= 0 W
= N
= 40 * (0.1 / 2) * 1 * 0.4747 * 50
= 47.47 mW
= 0 W
INPUTS
OUTPUTS
BLOCKS
+ P
OUTPUTS
* (
α
MEMORY
* P
* (
2
/ 2) * P
AC11
α
2
/ 2) *
BLOCKS
*
WRITE-CLOCK
READ-CLOCK
β
AC9
INPUTS
2
OUTPUTS
β
* F
α
β
* F
1
= 20
1
* P
2
READ-CLOCK
CLK
= 1 (100%)
β
= 0.1 (10%)
β
= 30
R e v i s i o n 1
AC10
3
2
= 0.125 (12.5%)
= 0.125 (12.5%)
= 40
= 10 MHz
= 10 MHz
* F
I/O
CLK
) + (N
BLOCKS
Actel Fusion Family of Mixed Signal FPGAs
* P
AC12
*
β
3
* F
WRITE-CLOCK
)
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