AFS600-PQG208 Actel, AFS600-PQG208 Datasheet - Page 225

• Manufacturer Part Number: AFS600-PQG208
• Description: FPGA - Field Programmable Gate Array 600K System Gates
• Manufacturer: Actel

Specifications of AFS600-PQG208

• Processor Series: AFS600
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 95
• Data Ram Size: 110592
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 600 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-159 • Minimum and Maximum DC Input and Output Levels
Figure 2-130 • AC Loading
Table 2-160 • AC Waveforms, Measuring Points, and Capacitive Loads
Table 2-161 • SSTL3 Class I
SSTL3 Class I
Drive
Strength
14 mA
Notes:
1. I
2. I
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
Input Low (V)
VREF – 0.2
Note:
Speed
Grade
Note:
Std.
–1
–2
larger when operating outside recommended ranges.
IL
IH
is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
*Measuring point = V
For the derating values at specific junction temperature and voltage supply levels, refer to
page
t
Commercial Temperature Range Conditions: T
Worst-Case VCCI = 3.0 V, VREF = 1.5 V
DOUT
0.66
0.56
0.49
SSTL3 Class I
Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). Fusion devices support Class
I. This provides a differential amplifier input buffer and a push-pull output buffer.
3-9.
Min.
–0.3 VREF – 0.2 VREF + 0.2
Timing Characteristics
V
Input High (V)
2.31
1.96
1.72
t
VREF + 0.2
DP
VIL
Max.
V
trip
0.04
0.04
0.03
t
. See
DIN
Table 2-87 on page 2-168
Min.
1.25
1.06
0.93
t
V
PY
Measuring Point* (V)
Test Point
VIH
t
0.43
0.36
0.32
EOUT
Max.
3.6
1.5
V
SSTL3
Class I
25
2.35
2.00
1.75
Max.
VOL
R e v i s i o n 1
t
0.7
ZL
V
J
for a complete table of trip points.
= 70°C, Worst-Case VCC = 1.425 V,
VTT
VCCI – 1.1
1.84
1.56
1.37
t
VREF (typ.) (V)
50
ZH
30 pF
VOH
Min.
V
1.5
t
LZ
Actel Fusion Family of Mixed Signal FPGAs
mA
I
14
OL
t
mA
HZ
I
14
OH
VTT (typ.) (V)
1.485
Max.
mA
I
OSL
54
4.59
3.90
3.42
t
ZLS
3
Max.
mA
I
OSH
51
3.46
3.04
t
4.07
ZHS
3
Table 3-7 on
C
LOAD
µA
I
10
IL
30
1
4
Units
(pF)
ns
ns
ns
2- 209
µA
I
10
IH
2
4