LIS3LV02DL STMicroelectronics, LIS3LV02DL Datasheet
LIS3LV02DL
Specifications of LIS3LV02DL
Available stocks
Related parts for LIS3LV02DL
LIS3LV02DL Summary of contents
Page 1
... The LIS3LV02DL is available in plastic SMD package and it is specified over a temperature range extending from -40°C to +85°C. The LIS3LV02DL belongs to a family of products suitable for a variety of applications: – Free-Fall detection – Motion activated functions in portable terminals – ...
Page 2
... Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1 I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1.1 5.2 SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2.1 5.2.2 5.2.3 6 Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2/48 SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 I2C - Inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Self test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SPI Read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 LIS3LV02DL ...
Page 3
... LIS3LV02DL 7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.1 WHO_AM_I (0Fh 7.2 OFFSET_X (16h 7.3 OFFSET_Y (17h 7.4 OFFSET_Z (18h 7.5 GAIN_X (19h 7.6 GAIN_Y (1Ah 7.7 GAIN_Z (1Bh 7.8 CTRL_REG1 (20h 7.9 CTRL_REG2 (21h 7.10 CTRL_REG3 (22h 7.11 HP_FILTER_RESET (23h 7.12 STATUS_REG (27h 7.13 OUTX_L (28h ...
Page 4
... Content 8 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.1 Mechanical characteristics at 25° 8.2 Mechanical characteristics derived from measurement in the -40°C to +85°C temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.3 Electro-mechanical characteristics at 25° Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4/48 LIS3LV02DL ...
Page 5
... LIS3LV02DL List of figures Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3. SPI slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 5. LIS3LV02DL electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 6. Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 7. SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 8. Multiple bytes SPI read protocol (2 bytes example Figure 9. SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 10. ...
Page 6
... Register description (27h Table 38. Register (28h Table 39. Register description (28h Table 40. Register (29h Table 41. Register description (29h Table 42. Register (2Ah Table 43. Register description (2Ah Table 44. Register (2Bh Table 45. Register description (2Bh Table 46. Register (2Ch Table 47. Register description (2Ch Table 48. Register (2Dh 6/48 LIS3LV02DL ...
Page 7
... LIS3LV02DL Table 49. Register description (2Dh Table 50. Register (30h Table 51. Register description (30h Table 52. Register (31h Table 53. Register description (31h Table 54. Register (34h Table 55. Register description (34h Table 56. Register (35h Table 57. Register description (35h Table 58. Register (36h Table 59. Register description (36h Table 60. ...
Page 8
... Data ready/inertial wake-up interrupt SDO SPI Serial Data Output Reconstruction Σ∆ Filter 2 I Reconstruction Regs Σ∆ Array Filter SPI Reconstruction Σ∆ Filter CONTROL LOGIC & CLOCK INTERRUPT GEN LIS3LV02DL 16 7 (TOP VIEW Function LIS3LV02DL CS SCL/SPC C SDA/SDO/SDI SDO RDY/INT GND RES ...
Page 9
... LIS3LV02DL Table 2. Pin description Pin Name 2 SDA Serial Data (SDA) SDI/ SPI Serial Data Input (SDI) SDO 3-wire Interface Serial Data Output (SDO) Vdd_IO Power supply for I/O pads Serial Clock (SCL) SCL/SPC SPI Serial Port Clock (SPC) SPI enable C/SPI mode selection (1: I ...
Page 10
... X, Y axis Full-scale = ± axis Full-scale = ± axis Full-scale = ± axis Full-scale = ± axis Full-scale = ± axis Full-scale = ± axis Full-scale = ± axis Max Delta from 25°C LIS3LV02DL (1) (2) Min. Max. Unit Typ. ±1.7 ±2.0 ±5.3 ±6.0 1.0 2.0 mg 3.9 15.6 ...
Page 11
... LIS3LV02DL Table 3. Mechanical characteristics @ Vdd=3.3 V, T=25 °C unless otherwise noted (continued) Symbol Parameter NL Non Linearity CrAx Cross axis V Self test output change st (9) BW System Bandwidth Operating Temperature Top Range Wh Product Weight 1. The product is factory calibrated at 3.3 V. The device can be used from 2. 3 ...
Page 12
... X, Y axis Full-scale = ±2g Z axis Full-scale = ± axis Full-scale = ±6g Z axis Full-scale = ± axis Full-scale = ±2g Z axis Full-scale = ± axis Full-scale = ±6g Z axis Max Delta from 25°C LIS3LV02DL (1) (2) Min. Max. Unit Typ. ±1.7 ±2.0 ±5.3 ±6.0 1.0 2.0 mg 3.9 15.6 ...
Page 13
... LIS3LV02DL Table 4. Mechanical characteristics @ Vdd=2.5 V, T=25 °C unless otherwise noted (continued) Symbol Parameter NL Non linearity CrAx Cross axis V Self test output change st (9) BW System bandwidth Top Operating temperature range Wh Product weight 1. The product is factory calibrated at 3.3 V. The device can be used from 2. 3 ...
Page 14
... Time to obtain valid data after exiting Power-Down mode 14/48 Test conditions Min. 2.16 1.71 Vdd = 3.3 V Vdd = 2.5 V 0.8*Vdd 0.9*Vdd Dec factor = 512 Dec factor = 128 Dec factor = 32 Dec factor = 8 LIS3LV02DL (1) (2) Max. Unit Typ. 3.3 3.6 V Vdd V 0.65 0.80 mA 0.60 0.75 µ ...
Page 15
... LIS3LV02DL 2.3 Communication interface characteristics 2.3.1 SPI - serial peripheral interface Subject to general operating conditions for Vdd and Top. Table 6. SPI Slave Timing Values Symbol tc(SPC) fc(SPC) tsu(CS) th(CS) tsu(SI) th(SI) tv(SO) th(SO) tdis(SO) 1. Values are guaranteed at 8 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production Figure 3 ...
Page 16
... I C fast mode Max Min Max 100 0 400 1.3 0.6 100 (2) 3.45 0.9 0 (3) 1000 300 20 + 0.1C b (3) 300 300 20 + 0.1C b 0.6 0.6 0.6 1.3 t su(SR) t w(SP:SR) t su(SP) LIS3LV02DL Unit KHz µs ns µs ns µs REPEATED START START STOP ...
Page 17
... LIS3LV02DL 2.4 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability ...
Page 18
... If the output signals change within the amplitude specified inside Table 3 interface chip are within the defined specification. 18/ then the sensor is working properly and the parameters of the LIS3LV02DL ...
Page 19
... Factor (DF) and spans from 2560 Hz. The acceleration data may be accessed through an I device particularly suitable for direct interfacing with a microcontroller. The LIS3LV02DL features a Data-Ready signal (RDY) which indicates when a new set of measured acceleration data is available thus simplifying data synchronization in digital system employing the device itself. ...
Page 20
... The trimming values are stored inside the device by a non volatile structure. Any time the device is turned on, the trimming parameters are downloaded into the registers to be employed during the normal operation. This allows the user to employ the device without further calibration. 20/48 LIS3LV02DL ...
Page 21
... LIS3LV02DL 4 Application hints Figure 5. LIS3LV02DL electrical connection Vdd_IO GND The device core is supplied through Vdd line while the I/O pads are supplied through Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 µF Al) should be placed as near as possible to the pin 13 of the device (common design practice). ...
Page 22
... Serial DAta line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both the lines are connected to Vdd_IO through a pull-up resistor embedded inside the LIS3LV02DL. When the bus is free both the lines are high. 2 ...
Page 23
... The I C embedded inside the LIS3LV02DL behaves like a slave device and the following protocol must be adhered to. After the start condition (ST) a salve address is sent, once a slave acknowledge (SAK) has been returned, a 8-bit sub-address will be transmitted: the 7 LSb represent the actual register address while the MSB enables address auto increment. If the MSb of the SUB field is 1, the SUB (register address) will be automatically incremented to allow multiple data read/write ...
Page 24
... In the presented communication format MAK is Master Acknowledge and NMAK is No Master Acknowledge. 5.2 SPI bus interface The LIS3LV02DL SPI is a bus slave. The SPI allows to write and read the registers of the device. The serial interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO. Figure 6. ...
Page 25
... LIS3LV02DL bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is read. In latter case, the chip will drive SDO at the start of bit 8. bit 1: MS bit. When 0, the address will remain unchanged in multiple read/write commands. ...
Page 26
... AD5 AD4 AD3 AD2 AD1 AD0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8 AD5 AD4 AD3 AD2 AD1 AD0 LIS3LV02DL DO15 DO14 DO13 DO12 DO11 DO10 DO9 DO8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 ...
Page 27
... LIS3LV02DL 5.2.3 SPI Read in 3-wires mode 3-wires mode is entered by setting to ‘1’ bit SIM (SPI Serial Interface Mode selection) in CTRL_REG2. Figure 11. SPI read protocol in 3-wires mode CS SPC SDI/O The SPI Read command is performed with 16 clock pulses: bit 0: READ bit. The value is 1. ...
Page 28
... LIS3LV02DL Default Comment Reserved 00111010 Dummy register Reserved Calibration Loaded at boot Calibration Loaded at boot Calibration Loaded at boot Calibration Loaded at boot Calibration Loaded at boot Calibration Loaded at boot Reserved 00000111 00000000 00001000 ...
Page 29
... LIS3LV02DL Table 15. Registers address map (continued) Register name Type FF_WU_THS_H rw FF_WU_DURATION rw DD_CFG rw DD_SRC rw DD_ACK r DD_THSI_L rw DD_THSI_H rw DD_THSE_L rw DD_THSE_H rw Registers marked as Reserved must not be changed. The writing to those registers may cause permanent damages to the device. The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values ...
Page 30
... WHO_AM_I (0Fh) Table 16. Register (0Fh Table 17. Register description (0Fh) W7, W0 LIS3LV02DL Physical Address equal to 3Ah Addressing this register the physical address of the device is returned. For LIS3LV02DL the physical address assigned in factory is 3Ah. 7.2 OFFSET_X (16h) Table 18. Register (16h) OX7 OX6 Table 19. ...
Page 31
... LIS3LV02DL Table 23. Register description (18h) OZ7, OZ0 Digital Offset Trimming for Z-Axis 7.5 GAIN_X (19h) Table 24. Register (19h) GX7 GX6 Table 25. Register description (19h) GX7, GX0 Digital Gain Trimming for X-Axis 7.6 GAIN_Y (1Ah) Table 26. Register (1Ah) GY7 GY6 Table 27. ...
Page 32
... MSB and LSB reading) Big/Little Endian selection BLE (0: little endian; 1: big endian) BOOT Reboot memory content Interrupt ENable IEN (0: data ready on RDY pad; 1: interrupt events on RDY pad) DRDY Enable Data-Ready generation 32/48 BLE BOOT IEN LIS3LV02DL DRDY SIM DAS ...
Page 33
... LIS3LV02DL Table 33. Register description (continued) (21h) SPI Serial Interface Mode selection SIM (0: 4-wire interface; 1: 3-wire interface) Data Alignment Selection DAS (0: 12 bit right justified bit left justified) FS bit is used to select Full Scale value. After the device power-up the default full scale value is +/-2g. In order to obtain a +/-6g full scale it is necessary to set FS bit to ‘ ...
Page 34
... Register description (27h) ZYXOR X, Y and Z axis Data Overrun ZOR Z axis Data Overrun YOR Y axis Data Overrun XOR X axis Data Overrun 34/48 HPFF FDS 0.318 -------------- - f = cutoff ZOR YOR XOR res res CFS1 ODRx ⋅ ---------------- - Hpc 2 ZYXDA ZDA YDA LIS3LV02DL CFS0 XDA ...
Page 35
... LIS3LV02DL Table 37. Register description (continued) (27h) ZYXDA X, Y and Z axis new Data Available ZDA Z axis new Data Available YDA Y axis new Data Available XDA X axis new Data Available The content of this register is updated every ODR cycle, regardless of BDU bit value in CTRL_REG2. ...
Page 36
... When reading the register in “12 bit right justified” mode the most significant bits (15:12) are replaced with bit 11 (i.e. ZD15-ZD12=ZD11, ZD11, ZD11, ZD11). 36/48 YD13 YD12 YD11 ZD5 ZD4 ZD3 ZD13 ZD12 ZD11 LIS3LV02DL YD10 YD9 YD8 ZD2 ZD1 ZD0 ZD10 ZD9 ZD8 ...
Page 37
... LIS3LV02DL In Big Endian Mode (bit BLE in CTRL_REG2 set to ‘1’) the content of this register is the LSB acceleration data. 7.19 FF_WU_CFG (30h) Table 50. Register (30h) AOI LIR Table 51. Register description (30h) And/Or combination of Interrupt events. Default value: 0. AOI (0: OR combination of interrupt events; ...
Page 38
... THS7, THS0 Free-fall / Inertial Wake Up Acceleration Threshold LSB 7.23 FF_WU_THS_H (35h) Table 56. Register (35h) THS15 THS14 Table 57. Register description (35h) THS15, THS8 38/48 THS5 THS4 THS13 THS12 Free-fall / Inertial Wake Up Acceleration Threshold MSB THS3 THS2 THS1 THS11 THS10 THS9 LIS3LV02DL THS0 THS8 ...
Page 39
... LIS3LV02DL 7.24 FF_WU_DURATION (36h) Table 58. Register (36h) FWD7 FWD6 Table 59. Register description (36h) FWD7, FWD0 This register sets the minimum duration of the free-fall/wake-up event to be recognized. 7.25 DD_CFG (38h) Table 60. Register (38h) IEND LIR Table 61. Register description (38h) Interrupt enable on Direction change. Default value: 0 IEND (0: disabled ...
Page 40
... Y accel. exceeding THSE threshold along negative direction of acceleration axis) X High. Default value (0: X below THSI threshold accel. exceeding THSE threshold along positive direction of acceleration axis) X Low. Default value (0: X below THSI threshold accel. exceeding THSE threshold along negative direction of acceleration axis) Direction detector source register. 40/ LIS3LV02DL ...
Page 41
... LIS3LV02DL 7.27 DD_ACK (3Ah) Dummy register. If LIR bit in DD_CFG register is set to ‘1’, a reading at this address allows the DD_SRC register refresh. Read data is not significant. 7.28 DD_THSI_L (3Ch) Table 64. Register (3Ch) THSI7 THSI6 Table 65. Register description (3Ch) THSI7, THSI0 7.29 DD_THSI_H (3Dh) Table 66 ...
Page 42
... Zero−g Level Offset [mg] 42/48 Figure 13. X-axis sensitivity at 3 940 Figure 15. Y-axis sensitivity at 3 940 LIS3LV02DL 960 980 1000 1020 1040 1060 1080 1100 Sensitivity [LSB/g] 960 980 1000 1020 1040 1060 1080 1100 Sensitivity [LSB/g] 1120 1120 ...
Page 43
... LIS3LV02DL Figure 16. Z-axis zero-g level at 3 −60 −40 −20 0 Zero−g Level Offset [mg] 8.2 Mechanical characteristics derived from measurement in the -40°C to +85°C temperature range Figure 18. X-axis zero-g level change vs. temperature at 3 −1.5 −1 −0.5 0 Zero−g Level drift [mg/ Figure 17. Z-axis Sensitivity at 3.3 V ...
Page 44
... C] Figure 25. Z axis zero-g level as function of 100 −20 −40 3 3.2 3.4 3.6 2 LIS3LV02DL temperature at 3.3 V −0.01 −0.005 0 0.005 0.01 0.015 o Sensitivity drift [%/ C] temperature at 3.3 V −0.04 −0.03 −0.02 −0.01 0 0.01 o Sensitivity drift [%/ C] supply voltage 2.2 2.4 2.6 2 ...
Page 45
... LIS3LV02DL Figure 26. Current consumption in Power- Down mode (Vdd=3 −5 −2.5 0 Current consumption [uA] Typical performance characteristics Figure 27. Current consumption in operational mode (Vdd=3 2.5 5 550 600 650 700 750 Current consumption [uA] 45/48 ...
Page 46
... seating plane Solder mask opening LIS3LV02DL ® trademark. OUTLINE AND MECHANICAL DATA LGA16 (4.4x7.5x1mm) Land Grid Array Package Detail 7863679 B ® ...
Page 47
... LIS3LV02DL 10 Revision history Table 72. Document revision history Date 15-Feb-2006 15-Jan-2008 Revision 1 Initial release. Added two new sections: Section 2.3: Communication interface characteristics 2 Typical performance Content reworked to improve readability Revision history Changes and characteristics. Section 8: 47/48 ...
Page 48
... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 48/48 Please Read Carefully: © 2008 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com LIS3LV02DL ...