STM32F100C6T6BTR STMicroelectronics, STM32F100C6T6BTR Datasheet - Page 56

• Manufacturer Part Number: STM32F100C6T6BTR
• Description: IC ARM CORTEX MCU 32KB 48LQFP
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32F100C6T6BTR

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 24MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: DMA, PDR, POR, PVD, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 10x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LFQFP
• Core: ARM Cortex M3
• For Use With: STM32100B-EVAL - EVAL BOARD FOR STM32F100VBT6
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Electrical characteristics
5.3.13
Table 34.
1. FT = 5V tolerant. To sustain a voltage higher than V
2. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by design, not tested in production.
3. With a minimum of 100 mV.
4. Leakage could be higher than max. if negative current is injected on adjacent pins.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
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Symbol
V
R
R
C
V
V
I
PMOS/NMOS contribution
lkg
hys
PU
PD
IH
IO
IL
Standard I/O input low
level voltage
I/O FT
level voltage
Standard I/O input
high level voltage
I/O FT
level voltage
Standard I/O Schmitt
trigger voltage
hysteresis
I/O FT Schmitt trigger
voltage hysteresis
Input leakage
current
Weak pull-up
equivalent resistor
Weak pull-down
equivalent resistor
I/O pin capacitance
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in
performed under the conditions summarized in
compliant.
I/O static characteristics
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in
in
Parameter
Figure 24
(1)
(1)
(4)
input low
input high
(2)
to the series resistance is minimum
and
(2)
(5)
(5)
Figure 25
V
Standard I/Os
SS
Conditions
V
V
V
V
V
DD
DD
≤
I/O FT
IN
IN
IN
V
=
=
= 5 V
IN
>
≤
V
V
2 V
2 V
for 5 V tolerant I/Os.
STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB
≤
SS
DD
V
DD
Doc ID 16455 Rev 6
DD
+0.3 the internal pull-up/pull-down resistors must be disabled.
0.41*(V
0.42*(V
(~10% order)
5% V
DD
–0.3
–0.3
Min
200
DD
–2 V) +1.3 V
30
30
Figure 22
DD
–2)+1 V
Table
(3)
.
Table 34
8. All I/Os are CMOS and TTL
and
Typ
40
40
5
Figure 23
are derived from tests
0.32*(V
0.28*(V
for standard I/Os, and
V
DD
DD
DD
Max
–2 V)+0.75 V
5.5
5.2
±1
50
50
–2 V)+0.8 V
3
+0.3
Unit
mV
mV
µA
kΩ
kΩ
pF
V