PCA9601D,118 NXP Semiconductors, PCA9601D,118 Datasheet - Page 18
![IC DUAL BI-DIR BUS BUFFER 8-SOIC](/photos/39/71/397193/inhouse_ca9601d118_t_sml.jpg)
PCA9601D,118
Manufacturer Part Number
PCA9601D,118
Description
IC DUAL BI-DIR BUS BUFFER 8-SOIC
Manufacturer
NXP Semiconductors
Datasheet
1.PCA9601D118.pdf
(31 pages)
Specifications of PCA9601D,118
Number Of Channels Per Chip
2
Supply Voltage (max)
15 V
Supply Voltage (min)
2.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
SO-8
Interface
I2C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-5303-2
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PCA9601D,118
Manufacturer:
NXP
Quantity:
5 600
NXP Semiconductors
PCA9601_1
Product data sheet
Fig 19. I
SDA
SCL
2
C-bus multipoint application
3.3 V to 5 V
3.3 V to 5 V
SX
SY
There is an Excel calculator which makes it easy to determine the maximum I
speed when using the PCA9601. The calculator and instructions can be found at
www.nxp.com/clockspeedcalculator.
PCA9601
The actual LOW period will be 407 + 126 = 533 ns, which exceeds the minimum Fm+
500 ns requirement. This system requires the bus LOW period, and therefore cycle
time, to be increased by 33 ns so the system must run slightly below the 1 MHz limit.
The possible maximum speed has a cycle period of 1033 ns or 968 kHz.
12 V
RX
RY
TX
TY
12 V
12 V
All information provided in this document is subject to legal disclaimers.
no limit to the number of connected bus devices
SX
PCA9601
SCL/SDA
Rev. 01 — 28 May 2010
SY
SX
PCA9601
SCL/SDA
SY
SX
PCA9601
SCL/SDA
SY
PCA9601
Dual bidirectional bus buffer
3.3 V 3.3 V
twisted-pair telephone wires,
USB, or flat ribbon cables;
up to 15 V logic levels,
include V
CC
PCA9601
© NXP B.V. 2010. All rights reserved.
and GND
SY SDA
SX SCL
2
002aae883
C-bus clock
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