pca9601 NXP Semiconductors, pca9601 Datasheet
pca9601
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pca9601 Summary of contents
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... Rev. 01 — 28 May 2010 1. General description The PCA9601 is designed to isolate I driven in point-to-point or multipoint applications 4000 pF. The PCA9601 is a higher-speed version of the P82B96 and a higher drive version of the PCA9600 that allows many more Fast-mode Plus (Fm+) slaves on remote daughter cards in applications with temperature range of 0 ° ...
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... PCA9601 −40 °C to +85 °C 9601 PCA9601 1 SX (SDA) static level offset card side 7 SY (SCL) Block diagram of PCA9601 All information provided in this document is subject to legal disclaimers. Rev. 01 — 28 May 2010 Dual bidirectional bus buffer 2 C-bus nodes (2 ...
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... C-bus (SDA or SCL) 8 positive supply voltage All information provided in this document is subject to legal disclaimers. Rev. 01 — 28 May 2010 PCA9601 Dual bidirectional bus buffer PCA9601DP GND 002aae875 Fig 3. Pin configuration for TSSOP8 (MSOP8) © NXP B.V. 2010. All rights reserved. V ...
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... Functional description Refer to The PCA9601 has two identical buffers allowing buffering of SDA and SCL I signals. Each buffer is made up of two logic signal paths, a forward path from the I interface, pins SX and SY which drive the buffered bus, and a reverse signal path from the buffered bus input, pins RX and RY to drive the I • ...
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... V 7.3 Connections to other bus buffers Two or more I/Os must not be interconnected. The PCA9601 design does not support this configuration. Bidirectional I pin so, instead, slightly different logic LOW voltage levels are used at SX/SY to avoid latching of this buffer. A ‘ ...
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... NXP Semiconductors 7.4 Comparison of PCA9601/PCA9600 and P82B96 The PCA9601 is a direct upgrade of the P82B96 with the significant differences summarized in Fast-mode Plus devices on the SX/SY sides. Table 4. PCA9601/PCA9600 versus P82B96 Detail Supply voltage (V ) range: CC Maximum operating bus voltage (independent Typical operating supply current: ...
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... When the operating temperature range is restricted at both limits typical output is well below 0.4 V and the P82B96 typically requires 0.6 V input even at +60 °C, so there is a reasonable margin. The PCA9601/PCA9600 requires a typical input low of 0 its typical margin is smaller °C the driver requires a typical input low of 1 ...
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... RX and RY; SX and SY HIGH or LOW 0 buffered bus input on RX and RY All information provided in this document is subject to legal disclaimers. Rev. 01 — 28 May 2010 PCA9601 Dual bidirectional bus buffer = 2 ° amb Min Typ Max 2 ...
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... SX and SY; SX output LOW at 0 input HIGH maximum SX, SY, TX and TY; voltage at which all buses are to be released at 25 °C Figure 9 All information provided in this document is subject to legal disclaimers. Rev. 01 — 28 May 2010 PCA9601 Dual bidirectional bus buffer = 2 ° ...
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... The maximum static sink current for a standard I holding the bus LOW. However, when an external device pulls the SX/SY pins below 1.4 V, the PCA9601 may source a current between 0 mA and 1 mA maximum. During contention an external device is required to pull the bus connected down to the 0.4 V ...
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... mA) OL 600 IH 500 400 300 200 −50 − changes over temperature range function of junction temperature; IH minimum values PCA9601 002aac840 100 125 T (°C) j 001aai061 100 125 T (°C) j © NXP B.V. 2010. All rights reserved ...
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... Dual bidirectional bus buffer 1000 I (1) 800 (2) 600 400 200 0 −50 − (1) Maximum. (2) Typical. junction temperature if these pins are externally pulled to 0 lower 002aaf484 (mA PCA9601 001aai062 75 100 125 T (°C) j © NXP B.V. 2010. All rights reserved ...
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... C-bus nodes via opto-couplers main enclosure 3 3 PCA9601 2 C-bus communication All information provided in this document is subject to legal disclaimers. Rev. 01 — 28 May 2010 PCA9601 Dual bidirectional bus buffer V (2 (SDA) 'SDA' (new levels) RX (SDA) ...
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... LOW speed period period (kHz) (ns) (ns) 600 3850 125 600 2450 195 260 770 620 260 720 690 PCA9601 V CC2 2 I C-BUS SLAVE(S) GND 002aae879 Max. slave response delay normal specification 400 kHz parts normal specification 400 kHz parts meets Fm+ ...
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... Rev. 01 — 28 May 2010 Dual bidirectional bus buffer remote slave bus Rs SCL SX PCA9601 Cs slave bus capacitance ) × 10V (ns). b CCB CCS buffered expansion bus Rb TX/RX TX/RX Cb buffered bus wiring capacitance 002aae881 PCA9601 V CCS SLAVE 2 I C-BUS 002aae880 © NXP B.V. 2010. All rights reserved ...
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... Cb master bus buffered bus capacitance wiring capacitance Figure 17, and Figure 18 show the PCA9601 used to drive extended bus wiring Figure Figure 18. 2 C-bus system is that a slave's data response (which is All information provided in this document is subject to legal disclaimers. Rev. 01 — 28 May 2010 PCA9601 ...
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... Example required to connect an Fm+ slave, with Rs × Cs product of 100 ns Fast-mode system also having 100 ns Rm × Cm using two PCA9601’s to buffer bus with 4 nF loading and 160 Ω pull-up. Calculate the allowed bus speed: Delay A = 120 + × ...
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... SX SDA 3 SCL PCA9601 2 Fig 19. I C-bus multipoint application There is an Excel calculator which makes it easy to determine the maximum I speed when using the PCA9601. The calculator and instructions can be found at www.nxp.com/clockspeedcalculator. PCA9601_1 Product data sheet PCA9601 ...
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... DC voltages will be applied. This ‘absolute maximum’ specification is intended continuous ratings and the nominal DC I even reach 0 V. Inside PCA9601 at every pin there is a large protective diode connected to the GND pin and that diode will start to conduct when the pin voltage is more than about − ...
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... V and we publish −0.3 V just to have some extra margin. Remark: You should not be concerned about the transients generated on the wiring by a PCA9601 in normal applications and that is input to the TX/RX or TY/RY pins of another PCA9601. Because not all ICs that may be driven by PCA9601 are designed to tolerate negative transients, in they can be managed if required ...
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... Example with questions and answers Question falling edge measure undershoot at −800 mV at the linked TX, RX pins of the PCA9601 that is generating the LOW, but the PCA9601 data sheet specifies minimum −0.3 V. Does this mean that we violate the data sheet absolute value? Answer: For PCA9601 the − ...
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... The duration of the undershoot is a function of the cable length and the input impedance of the connected IC. As shown in undershoot will be limited, by the diodes inside PCA9601, to around −0.8 V and that will not cause problems for PCA9601. Those transients will not be passed inside the IC to the SX/SY side of the IC ...
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... Is this a good idea? Answer: No not necessary to add any resistance. When the logic signal generated PCA9601 drives long traces or wiring with ICs other than PCA9601 being driven, then adding a Schottky diode (BAT54A) as shown in the wiring undershoot to a value that will not cause conduction of the IC’s internal diodes ...
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... Dual bidirectional bus buffer θ detail 6.2 1.0 0.7 1.05 0.25 0.25 5.8 0.4 0.6 0.039 0.028 0.041 0.01 0.01 0.016 0.024 EUROPEAN PROJECTION PCA9601 SOT96 (1) θ 0.7 0.1 0 0.028 0.004 0.012 ISSUE DATE 99-12-27 03-02-18 © NXP B.V. 2010. All rights reserved ...
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... All information provided in this document is subject to legal disclaimers. Rev. 01 — 28 May 2010 Dual bidirectional bus buffer θ detail 5.1 0.7 0.94 0.1 0.1 0.1 4.7 0.4 EUROPEAN PROJECTION PCA9601 SOT505 (1) θ Z 0.70 6° 0.35 0° ISSUE DATE 99-04-09 03-02-18 © NXP B.V. 2010. All rights reserved ...
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... Solder bath specifications, including temperature and impurities PCA9601_1 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 01 — 28 May 2010 PCA9601 Dual bidirectional bus buffer © NXP B.V. 2010. All rights reserved ...
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... Package reflow temperature (°C) 3 Volume (mm ) < 350 260 260 250 Figure 29. All information provided in this document is subject to legal disclaimers. Rev. 01 — 28 May 2010 PCA9601 Dual bidirectional bus buffer Figure 29) than a SnPb process, thus ≥ 350 220 220 350 to 2000 > 2000 260 260 250 ...
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... Serial Clock Line Serial DAta line System Management Bus Transistor-Transistor Logic Data sheet status Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 01 — 28 May 2010 PCA9601 Dual bidirectional bus buffer peak temperature Change notice Supersedes - - © NXP B.V. 2010. All rights reserved. ...
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... Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. All information provided in this document is subject to legal disclaimers. Rev. 01 — 28 May 2010 PCA9601 Dual bidirectional bus buffer © NXP B.V. 2010. All rights reserved ...
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... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 01 — 28 May 2010 PCA9601 Dual bidirectional bus buffer © NXP B.V. 2010. All rights reserved ...
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... Functional description . . . . . . . . . . . . . . . . . . . 4 7.1 Static level offset card side . . . . . . . . . . . . . . . . 4 7.1.1 Fast-mode operation . . . . . . . . . . . . . . . . . . . . 4 7.1.2 Fast-mode Plus operation . . . . . . . . . . . . . . . . 4 7.2 High drive, long distance side 7.3 Connections to other bus buffers . . . . . . . . . . . 5 7.4 Comparison of PCA9601/PCA9600 and P82B96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 Limiting values Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 8 10 Application information 10.1 Calculating system delays and bus clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 10.2 Negative undershoot below absolute minimum value ...