74VHC125D,118 NXP Semiconductors, 74VHC125D,118 Datasheet
74VHC125D,118
Specifications of 74VHC125D,118
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74VHC125D,118 Summary of contents
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Quad buffer/line driver; 3-state Rev. 02 — 13 October 2009 1. General description The 74VHC125; 74VHCT125 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard ...
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... NXP Semiconductors 4. Functional diagram 1OE 2OE 3OE 4OE mna228 Fig 1. Logic symbol 5. Pinning information 5.1 Pinning 74VHC125 74VHCT125 1 1OE 2OE GND 7 Fig 4. Pin configuration SO14 and TSSOP14 74VHC_VHCT125_2 Product data sheet EN1 mna229 Fig 2. IEC logic symbol 4OE 3OE 9 3A ...
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... NXP Semiconductors 5.2 Pin description Table 2. Pin description Symbol Pin 1OE, 2OE, 3OE, 4OE 1, 4, 10, 13 1A, 2A, 3A 1Y, 2Y, 3Y GND Functional description [1] Table 3. Function table Control nOE HIGH voltage level LOW voltage level don’t care high-impedance OFF-state. 7. Limiting values Table 4 ...
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... NXP Semiconductors 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/ V input transition rise and fall rate 9. Static characteristics Table 6. Static characteristics Voltages are referenced to GND (ground = 0 V) ...
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... NXP Semiconductors Table 6. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions C input I capacitance C output O capacitance For type 74VHCT125 V HIGH-level input voltage V LOW-level input voltage V HIGH-level output voltage 8 LOW-level output voltage 8 OFF-state per input pin output current V = 5.5 V ...
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... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; For test circuit see Figure Symbol Parameter Conditions For type 74VHC125 t propagation nA to nY; see pd delay enable time nOE to nY; see disable time nOE to nY; see dis 3.6 V ...
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... NXP Semiconductors Table 7. Dynamic characteristics GND = 0 V; For test circuit see Figure Symbol Parameter Conditions For type 74VHCT125 t propagation nA to nY; see pd delay enable time nOE to nY; see 4 5 disable time nOE to nY; see dis power pF dissipation V = GND capacitance [1] Typical values are measured at nominal supply voltage (V ...
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... NXP Semiconductors nOE input output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH Measurement points are given in V and V are typical voltage output levels that occur with the output load Fig 7. Enable and disable times Table 8. Measurement points Type Input V M 74VHC125 0.5V CC 74VHCT125 1 ...
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... NXP Semiconductors negative positive Test data is given in Table Definitions test circuit Termination resistance should be equal to output impedance Load capacitance including jig and probe capacitance Load resistance Test selection switch. Fig 8. Load circuit for switching times Table 9. Test data Type Input 74VHC125 ...
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... NXP Semiconductors 12. Package outline SO14: plastic small outline package; 14 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.01 0.069 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor LSTTL Low-power Schottky Transistor-Transistor Logic ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model CDM Charge-Device Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date 74VHC_VHCT125_2 20091013 • ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 3 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13 14 Revision history ...