74LVCH1T45GW,125 NXP Semiconductors, 74LVCH1T45GW,125 Datasheet - Page 23

• Manufacturer Part Number: 74LVCH1T45GW,125
• Description: TXRX XLATING DUAL 3ST SOT363
• Manufacturer: NXP Semiconductors

Specifications of 74LVCH1T45GW,125

• Logic Family: 74LVCH
• Number Of Channels Per Chip: 2
• Propagation Delay Time: 29.5 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.2 V
• Maximum Operating Temperature: + 125 C
• Package / Case: SC-88
• Maximum Power Dissipation: 250 mW
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-5494-2

NXP Semiconductors
74LVC_LVCH1T45
Product data sheet
14.2 Bidirectional logic level-shifting application
Figure 16
level-shifting application. Since the device does not have an output enable pin, the system
designer should take precautions to avoid bus contention between system-1 and
system-2 when changing directions.
Table 17
and then from system-2 to system-1.
Table 17.
[1]
State DIR CTRL I/O-1
1
2
3
4
Fig 16. Bidirectional logic level-shifting application
H = HIGH voltage level;
L = LOW voltage level;
Z = high-impedance OFF-state.
DIR CTRL
V
I/O-1
H
H
L
L
CC1
gives a sequence that will illustrate data transmission from system-1 to system-2
Pull-up or pull-down only needed for 74LVC1T45.
shows the 74LVC1T45; 74LVCH1T45 being used in a bidirectional logic
Description bidirectional logic level-shifting application
system-1
PULL-UP/DOWN
All information provided in this document is subject to legal disclaimers.
output
Z
Z
input
Rev. 3 — 19 August 2010
V
CC1
I/O-2
input
Z
Z
output
V
CC(A)
GND
A
74LVC1T45; 74LVCH1T45
1
2
3
Description
system-2 is getting ready to send data to system-1.
I/O-1 and I/O-2 are disabled. The bus-line state
depends on bus hold.
DIR bit is set LOW. I/O-1 and I/O-2 still are disabled.
The bus-line state depends on bus hold.
system-1 data to system-2
system-2 data to system-1
74LVCH1T45
74LVC1T45
Dual supply translating transceiver; 3-state
6
5
4
V
DIR
B
CC(B)
V
PULL-UP/DOWN
CC2
[1]
system-2
© NXP B.V. 2010. All rights reserved.
V
I/O-2
CC2
001aaj995
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