STM32W108B-SK STMicroelectronics, STM32W108B-SK Datasheet - Page 140

• Manufacturer Part Number: STM32W108B-SK
• Description: STARTER KIT FOR STM32W108
• Manufacturer: STMicroelectronics
• Series: STM32r
• Type: MCUr

Specifications of STM32W108B-SK

• Featured Product: STM32 Cortex-M3 Companion Products
• Contents: Board
• Silicon Manufacturer: ST Micro
• Core Architecture: ARM
• Core Sub-architecture: Cortex - M3
• Silicon Core Number: STM32
• Silicon Family Name: STM32W108xx
• Kit Contents: Board
• Features: IEEE
• Mfg Application Notes: STM32W108 Adjacent Channel Rejection Measurements
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

General-purpose timers
10.3.2
140/209
31
15
30
14
Timer x control register 2 (TIMx_CR2)
Address offset: 0xE004 (TIM1) and 0xF004 (TIM2)
Reset value:
Bit 1 TIM_UDIS: Update Disable
Bit 0 TIM_CEN: Counter Enable
Bit 7 TIM_TI1S: TI1 Selection
29
13
0: An update event is generated as soon as a counter overflow occurs, a software update is
generated, or a hardware reset is generated by the slave mode controller. Shadow registers are
then loaded with their buffer register values.
1: An update event is not generated and shadow registers keep their value (TIMx_ARR,
TIMx_PSC, TIMx_CCRy). The counter and the prescaler are reinitialized if the TIM_UG bit is
set or if a hardware reset is received from the slave mode controller.
0: Counter disabled.
1: Counter enabled.
Note: External clock, gated mode and encoder mode can work only if the TIM_CEN bit has
0: TI1M (input of the digital filter) is connected to TI1 input.
1: TI1M is connected to the TI_HALL inputs (XOR combination).
28
12
Reserved
been previously set by software. Trigger mode sets the TIM_CEN bit automatically
through hardware.
27
11
0x0000 0000
26
10
25
9
Doc ID 16252 Rev 8
24
8
Reserved
TIM_TI
1S
23
rw
7
22
6
TIM_MMS
rw
21
5
STM32W108CB, STM32W108HB
20
4
19
3
18
2
Reserved
17
1
16
0