STM32W108B-SK STMicroelectronics, STM32W108B-SK Datasheet - Page 58
STM32W108B-SK
Manufacturer Part Number
STM32W108B-SK
Description
STARTER KIT FOR STM32W108
Manufacturer
STMicroelectronics
Series
STM32r
Type
MCUr
Datasheets
1.STM32W108B-KEXT.pdf
(3 pages)
2.STM32W108B-KEXT.pdf
(209 pages)
3.STM32W108B-KEXT.pdf
(27 pages)
4.STM32W108B-KEXT.pdf
(6 pages)
5.STM32W108B-SK.pdf
(21 pages)
6.STM32W108B-KEXT.pdf
(14 pages)
7.STM32W108B-KEXT.pdf
(36 pages)
Specifications of STM32W108B-SK
Featured Product
STM32 Cortex-M3 Companion Products
Contents
Board
Silicon Manufacturer
ST Micro
Core Architecture
ARM
Core Sub-architecture
Cortex - M3
Silicon Core Number
STM32
Silicon Family Name
STM32W108xx
Kit Contents
Board
Features
IEEE
Mfg Application Notes
STM32W108 Adjacent Channel Rejection Measurements
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- STM32W108B-KEXT PDF datasheet
- STM32W108B-KEXT PDF datasheet #2
- STM32W108B-KEXT PDF datasheet #3
- STM32W108B-KEXT PDF datasheet #4
- STM32W108B-SK PDF datasheet #5
- STM32W108B-KEXT PDF datasheet #6
- STM32W108B-KEXT PDF datasheet #7
- Current page: 58 of 209
- Download datasheet (3Mb)
General-purpose input/outputs
8.1.4
8.1.5
Note:
58/209
Table 8.
Reset
A full chip reset is one due to power on (low or high voltage), the NRST pin, the watchdog, or
the SYSRESETREQ bit. A full chip reset affects the GPIO configuration as follows:
●
●
●
nBOOTMODE
nBOOTMODE is a special alternate function of PA5 that is active only during a pin reset
(NRST) or a power-on-reset of the always-powered domain (POR_HV). If nBOOTMODE is
asserted (pulled or driven low) when coming out of reset, the processor starts executing an
embedded serial boot loader instead of its normal program.
While in reset and during the subsequent power-on-reset startup delay (512 high-frequency
RC oscillator periods), PA5 is automatically configured as an input with a pull-up resistor. At
the end of this time, the STM32W108 samples nBOOTMODE: a high level selects normal
startup, and a low level selects the boot loader. After nBOOTMODE has been sampled, PA5
is configured as a floating input. The GPIO_BOOTMODE bit in the GPIO_DBGSTAT register
captures the state of nBOOTMODE so that software may act on this signal if required.
To avoid inadvertently asserting nBOOTMODE, PA5's capacitive load should not exceed
252 pF.
GPIO
PC0
PC2
PC3
PC4
PC4
PA7
The GPIO_PxCFGH/L configurations of all pins are configured as floating inputs.
The GPIO_EXTREGEN bit is set in the GPIO_DBGCFG register, which overrides the
normal configuration for PA7.
The GPIO_DEBUGDIS bit in the GPIO_DBGCFG register is cleared, allowing Serial
Wire/JTAG access to override the normal configuration of PC0, PC2, PC3, and PC4.
GPIO_EXTREGEN bit set in the
GPIO_DBGCFG register
Debugger interface is active in JTAG mode
Debugger interface is active in JTAG mode
Debugger interface is active in JTAG mode
Debugger interface is active in JTAG mode
Debugger interface is active in Serial Wire
mode
GPIO forced functions
Override condition
Doc ID 16252 Rev 8
Open-drain output
Input with pull up
Push-pull output
Input with pull up
Input with pull up
Bidirectional (push-pull
output or floating input)
controlled by debugger
interface
Forced function
STM32W108CB, STM32W108HB
Forced signal
REG_EN
SWDIO
JTDO
JTMS
JRST
JDTI
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