STM32W108B-SK STMicroelectronics, STM32W108B-SK Datasheet - Page 176

• Manufacturer Part Number: STM32W108B-SK
• Description: STARTER KIT FOR STM32W108
• Manufacturer: STMicroelectronics
• Series: STM32r
• Type: MCUr

Specifications of STM32W108B-SK

• Featured Product: STM32 Cortex-M3 Companion Products
• Contents: Board
• Silicon Manufacturer: ST Micro
• Core Architecture: ARM
• Core Sub-architecture: Cortex - M3
• Silicon Core Number: STM32
• Silicon Family Name: STM32W108xx
• Kit Contents: Board
• Features: IEEE
• Mfg Application Notes: STM32W108 Adjacent Channel Rejection Measurements
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Interrupts
12.3
12.3.1
176/209
INT_IR
QD
31
15
rw
INT_IR
QC
30
14
rw
Nested vectored interrupt controller (NVIC) interrupts
Top-level set interrupts configuration register (INT_CFGSET)
Address offset: 0x0100
Reset value:
Bit 16 INT_DEBUG: Write 1 to enable debug interrupt. (Writing 0 has no effect.)
Bit 15 INT_IRQD: Write 1 to enable IRQD interrupt. (Writing 0 has no effect.)
Bit 14 INT_IRQC: Write 1 to enable IRQC interrupt. (Writing 0 has no effect.)
Bit 13 INT_IRQB: Write 1 to enable IRQB interrupt. (Writing 0 has no effect.)
Bit 12 INT_IRQA: Write 1 to enable IRQA interrupt. (Writing 0 has no effect.)
Bit 11 INT_ADC: Write 1 to enable ADC interrupt. (Writing 0 has no effect.)
Bit 10 INT_MACRX: Write 1 to enable MAC receive interrupt. (Writing 0 has no effect.)
INT_IR
Bit 9 INT_MACTX: Write 1 to enable MAC transmit interrupt. (Writing 0 has no effect.)
Bit 8 INT_MACTMR: Write 1 to enable MAC timer interrupt. (Writing 0 has no effect.)
Bit 7 INT_SEC: Write 1 to enable security interrupt. (Writing 0 has no effect.)
Bit 6 INT_SC2: Write 1 to enable serial controller 2 interrupt. (Writing 0 has no effect.)
Bit 5 INT_SC1: Write 1 to enable serial controller 1 interrupt. (Writing 0 has no effect.)
Bit 4 INT_SLEEPTMR: Write 1 to enable sleep timer interrupt. (Writing 0 has no effect.)
Bit 3 INT_BB: Write 1 to enable baseband interrupt. (Writing 0 has no effect.)
Bit 2 INT_MGMT: Write 1 to enable management interrupt. (Writing 0 has no effect.)
Bit 1 INT_TIM2: Write 1 to enable timer 2 interrupt. (Writing 0 has no effect.)
Bit 0 INT_TIM1: Write 1 to enable timer 1 interrupt. (Writing 0 has no effect.)
QB
29
13
rw
INT_IR
QA
28
12
rw
INT_AD
27
11
rw
C
0x0000 0000
INT_MA
CRX
26
10
rw
INT_MA
CTX
25
rw
9
Doc ID 16252 Rev 8
Reserved
INT_MA
CTMR
24
rw
8
INT_SE
23
rw
C
7
INT_SC
22
rw
6
2
INT_SC
21
rw
5
1
STM32W108CB, STM32W108HB
EEPTM
INT_SL
20
rw
R
4
INT_BB
19
rw
3
INT_MG
MT
18
rw
2
INT_TI
M2
17
rw
1
INT_DE
INT_TI
BUG
M1
16
rw
rw
0