LAN9215-MT SMSC, LAN9215-MT Datasheet - Page 106

• Manufacturer Part Number: LAN9215-MT
• Description: CONTROLLER, ENET, NON-PCI, 100TQFP
• Manufacturer: SMSC

Specifications of LAN9215-MT

• Data Rate: 100Mbps
• No. Of Ports: 2
• Ethernet Type: IEEE 802.3 / 802.3u
• Supply Current: 40mA
• Supply Voltage Range: 2.97V To 3.63V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: TQFP
• Interface Type: HBI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 1.93 (12-12-07)
5.4.6
5.4.7
31-16
31-16
15-11
BITS
BITS
10-6
15-0
5-2
1
0
Reserved
PHY Address: Selects the external or internal PHY based on its address. The internal PHY is set to
address 00001b.
MII Register Index (MIIRINDA): These bits select the desired MII register in the PHY.
Reserved
MII Write (MIIWnR): Setting this bit tells the PHY that this will be a write operation using the MII data
register. If this bit is not set, this will be a read operation, packing the data in the MII data register.
MII Busy (MIIBZY): This bit must be polled to determine when the MII register access is complete.
This bit must read a logical 0 before writing to this register and MII data register.
The LAN driver software must set (1) this bit in order for the LAN9215i to read or write any of the MII
PHY registers.
During a MII register access, this bit will be set, signifying a read or write access is in progress. The
MII data register must be kept valid until the MAC clears this bit during a PHY write operation. The
MII data register is invalid until the MAC has cleared this bit during a PHY read operation.
Reserved
MII Data. This contains the 16-bit value read from the PHY read operation or the 16-bit data value to
be written to the PHY before an MII write operation.
MII_ACC—MII Access Register
This register is used to control the Management cycles to the PHY.
MII_DATA—MII Data Register
This register contains either the data to be written to the PHY register specified in the MII Access
Register, or the read data from the PHY register whose index is specified in the MII Access Register.
Offset:
Default Value:
Offset:
Default Value:
Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support
6
00000000h
7
00000000h
DATASHEET
106
DESCRIPTION
DESCRIPTION
Attribute:
Size:
Attribute:
Size:
R/W
32 bits
R/W
32 bits
SMSC
LAN9215i
Datasheet