IS61LV6416-10TL INTEGRATED SILICON SOLUTION (ISSI), IS61LV6416-10TL Datasheet

IC, SRAM, 1MBIT, 10NS, TSOP-2-44

IS61LV6416-10TL

Manufacturer Part Number
IS61LV6416-10TL
Description
IC, SRAM, 1MBIT, 10NS, TSOP-2-44
Manufacturer
INTEGRATED SILICON SOLUTION (ISSI)
Datasheet

Specifications of IS61LV6416-10TL

Memory Size
1Mbit
Memory Configuration
64K X 16
Access Time
10ns
Supply Voltage Range
3.135V To 3.6V
Memory Case Style
TSOP-2
No. Of Pins
44
Operating Temperature Range
0°C To +70°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Integrated Silicon Solution, Inc.
Rev. I
11/22/05
FEATURES
• High-speed access time: 8, 10, 12 ns
• CMOS low power operation
• TTL compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
• Lead-free available
FUNCTIONAL BLOCK DIAGRAM
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
64K x 16 HIGH-SPEED CMOS STATIC RAM
WITH 3.3V SUPPLY
IS61LV6416
IS61LV6416L
— 61LV6416:
— 61LV6416L:
required
75 mW (typical) operating current
65 mW (typical) operating current
0.5 mW (typical) standby current
50 µW (typical) standby current
Lower Byte
Upper Byte
I/O8-I/O15
I/O0-I/O7
A0-A15
V
GND
DD
WE
CE
OE
UB
LB
DECODER
CIRCUIT
CONTROL
CIRCUIT
DATA
I/O
DESCRIPTION
The
1,048,576-bit static RAM organized as 65,536 words by 16
bits. It is fabricated using
technology. This highly reliable process coupled with
innovative circuit design techniques, yields access times
as fast as 8 ns with low power consumption.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip
Enable and Output Enable inputs, CE and OE. The active
LOW Write Enable (WE) controls both writing and reading
of the memory. A data byte allows Upper Byte (UB) and
Lower Byte (LB) access.
The IS61LV6416/IS61LV6416L is packaged in the JEDEC
standard 44-pin 400-mil SOJ, 44-pin TSOP-II, and 48-pin
mini BGA (6mm x 8mm).
ISSI
MEMORY ARRAY
IS61LV6416/IS61LV6416L is a high-speed,
COLUMN I/O
64K x 16
ISSI
's high-performance CMOS
ISSI
NOVEMBER 2005
1
®

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IS61LV6416-10TL Summary of contents

Page 1

... Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS61LV6416/IS61LV6416L is packaged in the JEDEC standard 44-pin 400-mil SOJ, 44-pin TSOP-II, and 48-pin mini BGA (6mm x 8mm). A0-A15 ...

Page 2

... IS61LV6416 IS61LV6416L PIN CONFIGURATIONS 44-Pin SOJ (K) A15 A14 A13 A12 A11 I/ I/O15 I/ I/O14 I/ I/O13 I/ I/O12 VDD 11 34 GND GND 12 33 VDD I/ I/O11 I/ I/O10 I/ I/ A10 48-Pin mini BGA (6mm x 8mm) ( I I/O A6 I/O A5 I/O I GND NC A7 I I/O ...

Page 3

... IS61LV6416 IS61LV6416L TRUTH TABLE Mode Not Selected X Output Disabled H X Read Write ABSOLUTE MAXIMUM RATINGS Symbol Parameter V Terminal Voltage with Respect to GND TERM T Storage Temperature STG P Power Dissipation Output Current (LOW) OUT Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device ...

Page 4

... CE ≥ V Current (CMOS Inputs) ≥ ≤ 0.2V Note address and data inputs are cycling at the maximum frequency means no input lines change. MAX 2. Typical values are measured IS61LV6416L POWER SUPPLY CHARACTERISTICS Symbol Parameter Test Conditions I V Dynamic Operating Supply Current I OUT I TTL Standby Current ...

Page 5

... IS61LV6416 IS61LV6416L AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load AC TEST LOADS 319 Ω 3.3V OUTPUT 30 pF Including jig and scope Figure 1a. READ CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Read Cycle Time ...

Page 6

... IS61LV6416 IS61LV6416L AC WAVEFORMS (Address Controlled) ( (1,2) READ CYCLE NO. 1 ADDRESS D OUT PREVIOUS DATA VALID READ CYCLE NO. 2 (1,3) ADDRESS LZCE LB LZB HIGH-Z D OUT Notes HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB Address is valid prior to or coincident with CE LOW transition. ...

Page 7

... IS61LV6416 IS61LV6416L WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Write Cycle Time Write End t SCE t Address Setup Time AW to Write End t Address Hold from Write End HA t Address Setup Time SA LB, UB Valid to End of Write t PBW WE Pulse Width (OE = HIGH/LOW PWE PWE t Data Setup to Write End ...

Page 8

... IS61LV6416 IS61LV6416L (CE Controlled HIGH or LOW) (1,2) WRITE CYCLE NO. 1 ADDRESS UB DATA UNDEFINED OUT VALID ADDRESS t SCE PWE1 t PWE2 t PBW t HZWE HIGH DATA VALID IN ISSI ® LZWE HD UB_CEWR1.eps Integrated Silicon Solution, Inc. Rev. I 11/22/05 ...

Page 9

... IS61LV6416 IS61LV6416L (WE Controlled HIGH during Write Cycle) WRITE CYCLE NO. 2 (1) ADDRESS OE CE LOW UB DATA UNDEFINED OUT D IN WRITE CYCLE NO. 3 (WE Controlled LOW During Write Cycle) ADDRESS OE LOW CE LOW UB DATA UNDEFINED OUT D IN Integrated Silicon Solution, Inc. Rev. I 11/22/ VALID ADDRESS t AW ...

Page 10

... IS61LV6416 IS61LV6416L (LB, UB Controlled, Back-to-Back Write) WRITE CYCLE NO. 4 ADDRESS OE CE LOW WE UB HZWE D OUT DATA UNDEFINED D IN Notes: 1. The internal Write time is defined by the overlap LOW, UB and/ LOW, and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The referenced to the rising or falling edge of the signal that terminates the Write ...

Page 11

... GND Integrated Silicon Solution, Inc. Rev. I 11/22/05 Test Condition Options See Data Retention Waveform = 2.0V, CE ≥ – 0.2V IS61LV6416 DD DD IS61LV6416L See Data Retention Waveform See Data Retention Waveform = 3.0V and not 100% tested (CE Controlled) t Data Retention Mode SDR CE ≥ 0.2V ...

Page 12

... IS61LV6416 IS61LV6416L IS61LV6416 ORDERING INFORMATION Speed (ns) Order Part No. 8 IS61LV6416-8T 8 IS61LV6416-8TL 8 IS61LV6416-8BI 8 IS61LV6416-8TI 8 IS61LV6416-8KL 10 IS61LV6416-10T 10 IS61LV6416-10TL 10 IS61LV6416-10K 10 IS61LV6416-10BI 10 IS61LV6416-10BLI 10 IS61LV6416-10TI 10 IS61LV6416-10TLI 10 IS61LV6416-10KI 10 IS61LV6416-10KLI 12 IS61LV6416-12T 12 IS61LV6416-12K 12 IS61LV6416-12KL 12 IS61LV6416-12BI IS61LV6416L ORDERING INFORMATION Speed (ns) Order Part No. 8 IS61LV6416L-8T 8 IS61LV6416L-8BI 8 IS61LV6416L-8TI 8 IS61LV6416L-8KI 10 IS61LV6416L-10T 10 IS61LV6416L-10BI 10 IS61LV6416L-10TI ...

Page 13

PACKAGING INFORMATION 400-mil Plastic SOJ Package Code Millimeters Inches Symbol Min Max Min No. Leads ( 3.25 3.75 0.128 0.148 A1 0.64 — 0.025 A2 2.08 — 0.082 B 0.38 0.51 0.015 0.020 ...

Page 14

PACKAGING INFORMATION Millimeters Inches Symbol Min Max Min No. Leads ( 3.25 3.75 0.128 0.148 A1 0.64 — 0.025 A2 2.08 — 0.082 B 0.38 0.51 0.015 0.020 b 0.66 0.81 0.026 0.032 C 0.18 0.33 0.007 0.013 ...

Page 15

PACKAGING INFORMATION Mini Ball Grid Array Package Code: B (48-pin) Top View SEATING PLANE mBGA - 6mm x 8mm MILLIMETERS Sym. Min. Typ. Max. Min. Typ. ...

Page 16

PACKAGING INFORMATION Plastic TSOP Package Code: T (Type II Millimeters Inches Symbol Min Max Min Ref. Std. No. Leads ( — 1.20 — A1 0.05 0.15 0.002 0.006 b 0.30 0.52 0.012 ...

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