IS42S32800B-7TL INTEGRATED SILICON SOLUTION (ISSI), IS42S32800B-7TL Datasheet

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IS42S32800B-7TL

Manufacturer Part Number
IS42S32800B-7TL
Description
IC, SDRAM, 256MBIT, 143MHZ, TSOP-86
Manufacturer
INTEGRATED SILICON SOLUTION (ISSI)
Datasheet

Specifications of IS42S32800B-7TL

Memory Type
DRAM - Sychronous
Access Time
7ns
Page Size
256Mbit
Memory Case Style
TSOP
No. Of Pins
86
Operating Temperature Range
-40°C To +85°C
Frequency
143MHz
Termination Type
SMD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
2M Words x 32 Bits x 4 Banks (256-MBIT)
SYNCHRONOUS DYNAMIC RAM
FEATURES
· Concurrent auto precharge
· Clock rate:166/143 MHz
· Fully synchronous operation
· Internal pipelined architecture
· Four internal banks (2M x 32bit x 4bank)
· Programmable Mode
· Burst stop function
· Individual byte controlled by DQM0-3
· Auto Refresh and Self Refresh
· 4096 refresh cycles/64ms (15.6 s/row)
· 4096 refresh cycles/32ms for industrial grade
· Single +3.3V ±0.3V power supply
· Interface:LVTTL
· Package: 86 Pin TSOP-2,0.50mm Pin Pitch
· Pb-free package is available.
IS42S32800B
Integrated Silicon Solution, Inc.
Rev. F
07/21/09
-CAS#Latency:2 or 3
-Burst Length:1,2,4,8,or full page
-Burst Type:interleaved or linear burst
-Burst-Read-Single-Write
8x13mm, 90 Ball LF-BGA, Ball pitch 0.8mm
DESCRIPTION
The ISSI IS42S32800B is a high-speed CMOS
configured as a quad 2M x 32 DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal,CLK).
Each of the 2M x 32 bit banks is organized as 4096 rows
by 512 columns by 32 bits.Read and write accesses start
at a selected locations in a programmed sequence.
Accesses begin with the registration of a BankActive
command which is then followed by a Read or Write
command
The ISSI IS42S32800B provides for programmable
Read or Write burst lengths of 1,2,4,8,or full page, with
a burst termination operation. An auto precharge
function may be enable to provide a self-timed row
precharge that is initiated at the end of the burst
sequence.The refresh functions, either Auto or
Self Refresh are easy to use.
By having a programmable mode register,the system
can choose the most suitable modes to maximize its
performance.
These devices are well suited for applications requiring
high memory bandwidth.
JULY 2009
1

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IS42S32800B-7TL Summary of contents

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... Pb-free package is available. Integrated Silicon Solution, Inc. Rev. F 07/21/09 DESCRIPTION The ISSI IS42S32800B is a high-speed CMOS configured as a quad DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal,CLK). Each of the bit banks is organized as 4096 rows by 512 columns by 32 bits ...

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... IS42S32800B FUNCTIONAL BLOCK DIAGRAM CLK COMMAND COLUMN Integrated Silicon Solution, Inc Sense Amplifier Sense Amplifier Col um n Decoder Column Decoder 4096 X 512 X 32 CELL ARRAY (BANK #2) Sense Amplifier Sense Amplifier 4096 X 512 X 32 CELL ARRAY (BANK #3) Column Decoder Rev. F 07/21/09 ...

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... IS42S32800B PIN DESCRIPTIONS Table 1.Pin Details of IS42S32800B Symbol Type Description CLK Input Clock:CLK is driven by the system clock.All SDRAM input signals are sampled on the positive edge of CLK.CLK also increments the internal burst counter and controls the output registers. CKE Input Clock Enable:CKE activates(HIGH)and deactivates(LOW)the CLK signal.If CKE goes low syn- ...

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... IS42S32800B PIN CONFIGURATIONS 86 pin TSOP - Type II for x32 DQM0 DQM2 DQ16 V DQ17 DQ18 V DQ19 DQ20 V DQ21 DQ22 V DQ23 PIN DESCRIPTIONS A0-A11 Row Address Input A0-A8 Column Address Input BA0, BA1 Bank Select Address DQ0 to DQ31 Data I/O CLK System Clock Input ...

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... IS42S32800B PIN CONFIGURATION PACKAGE CODE BALL LF-BGA (Top View) (8. 13.00 mm Body, 0.8 mm Ball Pitch PIN DESCRIPTIONS A0-A11 Row Address Input A0-A8 Column Address Input BA0, BA1 Bank Select Address DQ0 to DQ31 Data I/O CLK System Clock Input CKE Clock Enable CS Chip Select ...

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... IS42S32800B Operation Mode Fully synchronous operations are performed to latch the commands at the positive edges of CLK.Table 2 shows the truth table for the operation commands. Table 2.Truth Table (Note (1),(2)) Command State BankActivate Idle BankPrecharge Any PrechargeAll Any Write Active Write and Auto Precharge Active ...

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... IS42S32800B I Commands 1 BankActivate (RAS#=”L”,CAS#=”H”,WE#=”H”,BS =Bank,A0-A11 =Row Address) The BankActivate command activates the idle bank designated by the BS0,1 (Bank Select) signal.By latching the row address A11 at the time of this command,the selected row access is initiated.The read or write operation in the same bank can occur after a time delay of tRCD(min ...

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... IS42S32800B 3 PrechargeAll command (RAS#=”L”,CAS#=”H”,WE#=”L”,BS =Don t care,A10 =”H”) The Precharge All command precharges all the four banks simultaneously and can be issued even if all banks are not in the active state. All banks are then switched to the idle state. ...

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... IS42S32800B T0 T1 CLK COMMAND READ A NOP CAS# latency=2 t CK2 , DQ s CAS# latency=3 t CK3 , DQ s Burst Read Operation(Burst Length =4,CAS#Latency =2,3) The read data appears on the DQs subject to the values on the DQM inputs two clocks earlier (i.e.DQM latency is two clocks for output buffers). A read burst without the auto precharge function may be interrupted by a subsequent Read or Write command to the same bank or the other active bank before the end of the burst length ...

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... IS42S32800B T0 T1 CLK COMMAND NOP READ A DQ’s : "H" or "L" Read to Write Interval (Burst Length = 4,CAS#Latency = CLK DQM COMMAND NOP NOP CAS# latency=2 tCK2, DQs : "H" or "L" Read to Write Interval (Burst Length = 4,CAS#Latency = CLK DQM COMMAND NOP NOP CAS# latency=2 t CK2 , DQ’s tCK2, DQs : " ...

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... IS42S32800B I T0 CLK Bank, ADDRESS Col A COMMAND READ A CAS# latency=2 t CK2 , DQ s CAS# latency=3 t CK3 , DQ s Read to Precharge (CAS#Latency =2,3) 5 Write command (RAS#=”H”,CAS#=”L”,WE#=”L”,BS =Bank,A10 =”L”,A0-A8 =Column Address) The Write command is used to write a burst of data on consecutive clock cycles from an active row in an active bank ...

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... IS42S32800B T0 T1 CLK WRITEA COMMAND NOP 1 Clk Interval DIN A 0 DQ’s Write Interrupted by a Write (Burst Length =4,CAS#Latency =2,3) The Read command that interrupts a write burst without auto precharge function should be issued one cycle after the clock edge in which the last data-in element is registered.In order to avoid data contention,input data must be removed from the DQs at least one clock cycle before the first read data appears on the outputs (refer to the following figure) ...

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... IS42S32800B 6 Concurrent Auto Precharge An access command (READ or WRITE) to another bank while an access command with auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM supports CONCURRENT AUTO PRECHARGE. ICSI SDRAMs support CONCURRENT AUTO PRECHARGE. Four cases where CONCURRENT AUTO PRECHARGE occurs are defined below. ...

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... IS42S32800B WRITE with Auto Precharge · Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out ap- pearing CAS latency later. The PRECHARGE to bank n will begin after met, where t WR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m ...

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... IS42S32800B 7 Mode Register Set command (RAS#=”L”,CAS#=”L”,WE#=”L”,BS0,1 and A11-A0 =Register Data) The mode register stores the data for controlling the various operating modes of SDRAM.The Mode Register Set command programs the values of CAS#latency,Addressing Mode and Burst Length in the Mode register to make SDRAM useful for a variety of different applications.The default values of the Mode Register after power-up are undefined ...

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... I IS42S32800B T0 T1 CLK t CK2 CKE CS# RAS# CAS# WE# ADDR. DQM Hi-Z DQ Precharge All The mode register is divided into various fields depending on functionality. Address BS0,1 A11/A10 Function RFU* *Note:RFU (Reserved for future use)should stay 0 during MRS cycle. Burst Length Field (A2~A0) ¡D ¡D ¡ ...

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... IS42S32800B • Burst Type Field (A3) The Burst Type can be one of two modes,Interleave Mode or Sequential Mode. A3 Burst Type 0 Sequential 1 Interleave —Addressing Sequence of Sequential Mode An internal column address is performed by increasing the address from the column address which is input to the device.The internal column address is varied by the Burst Length as shown in the following table.When the value of column address,(n +m),in the table is larger than 255,only the least significant 8 bits are effective ...

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... IS42S32800B I • Test Mode field (A8~A7) These two bits are used to enter the test mode and must be programmed to “00”in normal operation • Write Burst Length (A9) This bit is used to select the burst write length. A9 Write Burst Length 0 Burst 1 Single Bit 8 No-Operation command (RAS#=” ...

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... IS42S32800B 10 Device Deselect command (CS#=”H”) The Device Deselect command disables the command decoder so that the RAS#,CAS#,WE# and Address inputs are ignored,regardless of whether the CLK is enabled.This command is similar to the No Operation command. 11 AutoRefresh command (RAS#=”L”,CAS#=”L”,WE#=”H”,CKE =”H”) The AutoRefresh command is used during normal operation of the SDRAM and is analogous to CAS#-before- RAS#(CBR)Refresh in conventional DRAMs ...

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... I IS42S32800B ABSOLUTE MAXIMUM RATINGS Symbol Parameters V Supply Voltage (with respect Supply Voltage for Output (with respect to V DDQ V Input Voltage (with respect Output Voltage O I Short circuit output current O P Power Dissipation ( D T Operating Temperature OPT T Storage Temperature STG Notes: 1. Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification ...

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... IS42S32800B D.C. Electrical Characteristics (Recommended Operating Conditions) Description/Test condition Operating Current t t (min), Outputs Open, Input RC RC signal one transition per one cycle Precharge Standby Current in power down mode t = 15ns, CKE V (max Precharge Standby Current in power down mode CKE V (max Precharge Standby Current in non-power down mode ...

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... IS42S32800B E AC Electrical Characteristics (Recommended Operating Conditions) Symbol A.C. Parameter t Row cycle time RC (same bank) t Row activate to row activate delay RRD (different banks) t RAS# to CAS# delay RCD (same bank) t Precharge to refresh/row activate command RP (same bank) t Row activate to precharge time RAS (same bank) ...

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... IS42S32800B (N otes Continued) 6. A.C. Test Conditions LVTTL Interface Reference Level of Output Signals Output Load Input Signal Levels Transition Time (Rise and Fall)of Input Signals Reference Level of Input Signals Z0= 50Ω Output LVTTL A.C. Test Load 7. Transition times are measured between VIH and VIL.Transition(rise and fall)of input signals are in a fixed slope (1 ns) ...

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... IS42S32800B I Timing Waveforms Figure 1.AC Parameters for Write Timing (Burst Length=4,CAS#Latency= CLK CKE CS# RAS# CAS# WE# BS0 ADDR. RBx DQM t Hi-Z DQ Activate Command Bank T10 T11 t CK2 Begin Auto Precharge Begin Auto Precharge Bank A Bank RBx CAx CBx RAy CAy t DAL RCD ...

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... IS42S32800B Figure 2.AC Parameters for Read Timing (Burst Length=2,CAS#Latency= CLK CKE t IS CS# RAS# CAS# WE# BS0,1 A10 RAx t IS A0-A9 RAx DQM Hi-Z DQ Activate Command Bank A Integrated Silicon Solution, Inc. Rev. F 07/21/ CK2 RBx CAx RBx t RRD t RAS AC2 t AC2 t HZ RCD ...

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... IS42S32800B Figure 3.Auto Refresh (CBR)(Burst Length=4,CAS#Latency= CLK t CK2 CKE CS# RAS# CAS# WE# BS0,1 A10 A0- DQM DQ DQ Precharge All Auto Refresh Command Command T10 T11 T12 T13 T14 Auto Refresh Activate Command Command Bank A T15 T16 T17 T18 T19 T20 T21 T22 ...

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... IS42S32800B Figure 4.Power on Sequene and Auto Refresh (CBR CLK High level CKE is required CS RAS CAS WE BS0, 1 A10 ADD DQM High Level is Necessary t RP Hi-Z DQ Precharge 1st Auto Command Inputs Refresh All Banks Command must be stable for 200us Integrated Silicon Solution, Inc. ...

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... IS42S32800B I Figure 5.Self Refresh Entry &Exit Cycle CLK *Note 2 *Note 1 CKE t IS CS# RAS# *Note 8 CAS# BS0,1 A0-A9 WE# DQM Hi-Z DQ SelfRefresh Enter Note:To Enter SelfRefresh Mode 1. CS#,RAS#&CAS#with CKE should be low at the same clock cycle. 2. After 1 clock cycle,all the inputs including the system clock can be don ’t care except for CKE. ...

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... IS42S32800B Figure 6.2.Clock Suspension During Burst Read (Using CKE) (Burst Length=4,CAS#Latency= CLK t CK2 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx A0-A9 RAx CAx DQM DQ Hi-Z Activate Read Command Command Bank A Bank A Note:CKE to CLK disable/enable =1 clock Integrated Silicon Solution, Inc. Rev. F 07/21/ T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...

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... IS42S32800B I Figure 6.3.Clock Suspension During Burst Read (Using CKE) (Burst Length=4,CAS#Latency= CLK t CK3 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx A0-A9 CAx RAx DQM DQ Hi-Z Hi-Z Read Activate Command Command Bank A Bank A Note:CKE to CLK disable/enable =1 clock T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...

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... IS42S32800B Figure 7.2.Clock Suspension During Burst Write (Using CKE) (Burst Length=4,CAS#Latency= CLK t CK2 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx A0-A9 RAx CAx DQM Hi-Z DQ DAx0 Clock Suspend Activate 1 Cycle Command Bank A Write Command Bank A Note:CKE to CLK disable/enable =1 clock Integrated Silicon Solution, Inc. ...

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... IS42S32800B I Figure 7.3.Clock Suspension During Burst Write (Using CKE) (Burst Length=4,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx A0-A9 RAx CAx DQM DQ Hi-Z DAx0 Clock Suspend Activate ...

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... IS42S32800B Figure 8.Power Down Mode and Clock Mask (Burst Lenght=4, CAS#Latency= CLK t CK2 t IS CKE CS# RAS# CAS# WE# BS0,1 RAx A10 A0-A9 RAx DQM Hi-Z DQ ACTIVE STANDBY Activate Command Bank A Power Down Power Down Mode Entry Mode Exit Integrated Silicon Solution, Inc. ...

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... IS42S32800B Figure 9.2.Random Column Read (Page within same Bank) (Burst Length=4,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS# RAS# CAS# WE# BA0,1 A10 RAw A0-A9 RAw CAw DQM Hi-Z DQ Activate Read Command Command ...

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... IS42S32800B Figure 9.3.Random Column Read (Page within same Bank) (Burst Length=4,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS# RAS# CAS# WE# BS0,1 A10 RAw A0-A9 RAw CAw DQM Hi-Z DQ Activate Read Command Command ...

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... IS42S32800B Figure 10.2.Random Column Write (Page within same Bank) (Burst Length=4,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS# RAS# CAS# WE# BS0,1 RBw A10 A0-A9 CBw RBw DQM Hi-Z DQ DBw0 DBw1 DBw2 DBw3 ...

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... IS42S32800B Figure 10.3.Random Column Write (Page within same Bank) (Burst Length=4,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T2 2 CLK t CK3 CKE CS# RAS# CAS# WE# BS0,1 A10 RBw A 0-A9 CBw RBw DQM Hi-Z DBw0 DQ Activate Write Command ...

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... IS42S32800B Figure 11.3.Random Row Read (Interleaving Banks) (Burst Length=8,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 High CKE CS# RAS# CAS# WE# BS0,1 RBx A10 RBx CBx A0- RCD AC3 DQM Hi-Z DQ Activate Read Command Command ...

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... IS42S32800B Figure 12.2.Random Row Write (Interleaving Banks) (Burst Length=8,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE High CS# RAS# CAS# WE# BS0,1 A10 RAx A0-A9 RAx CAx t RCD DQM Hi-Z DQ DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 ...

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... IS42S32800B Figure 12.3.Random Row Write (Interleaving Banks) (Burst Length=8,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 High CKE CS# RAS# CAS# WE# BS0,1 A10 RAx RAx CAx A0-A9 t RCD DQM Hi-Z DQ DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 ...

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... IS42S32800B Figure 13.2.Read and Write Cycle (Burst Length=4,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx A0-A9 RAx CAx DQM Hi-Z DQ Read Activate Command Command Bank A Bank A Integrated Silicon Solution, Inc. ...

Page 42

... IS42S32800B Figure 13.3.Read and Write Cycle (Burst Length=4,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx A 0-A9 CAx RAx DQM Hi-Z DQ Activate Read Command Command Bank A Bank A 42 ...

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... IS42S32800B Figure 14.2.Interleaving Column Read Cycle (Burst Length=4,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS# RAS# CAS# WE# BS0,1 RAx A10 A 0-A9 RAx CAy t t RCD AC2 DQM Hi-Z DQ Read Activate Activate Command ...

Page 44

... IS42S32800B Figure 14.3.Interleaved Column Read Cycle (Burst Length=4,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS# RAS# CAS# WE# BS0,1 RAx A10 RAx CAx A0-A9 t RCD DQM DQ Hi-Z Read Activate Command Command Bank A Bank A ...

Page 45

... IS42S32800B Figure 15.2.Interleaved Column Write Cycle (Burst Length=4,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS# RAS# CAS# WE# BS0,1 RAx A10 RAx CAx A0-A9 t RCD DQM t RRD Hi-Z DAx0 DAx1 DAx2 DAx3 DQ Write ...

Page 46

... IS42S32800B Figure 15.3.Interleaved Column Write Cycle (Burst Length=4,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS# RAS# CAS# WE# BS0,1 RAx A10 RAx CAx RBw A 0-A9 t RCD DQM t > t RRD RRD(min) Hi-Z DQ DAx0 DAx1 DAx2 DAx3 ...

Page 47

... IS42S32800B Figure 16.2.Auto Precharge after Read Burst (Burst Length=4,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 High CKE CS# RAS# CAS# WE# BS0,1 RAx RBx A10 RBx RAx CAx A 0-A9 DQM Hi-Z DQ Ax0 Activate Activate ...

Page 48

... IS42S32800B Figure 16.3.Auto Precharge after Read Burst (Burst Length=4,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 High CKE CS# RAS# CAS# WE# BS0,1 RAx A10 CAx RAx A 0-A9 DQM Hi-Z DQ Activate Command Bank A Read Command ...

Page 49

... IS42S32800B Figure 17.2.Auto Precharge after Write Burst (Burst Length=4,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 High CKE CS# RAS# CAS# WE# BS0,1 RAx RBx A10 A0-A9 CAx RAx RBx DQM Hi-Z DQ DAx0 DAx1 DAx2 DAx3 ...

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... IS42S32800B Figure 17.3.Auto Precharge after Write Burst (Burst Length=4,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 High CKE CS# RAS# CAS# WE# BS0,1 RBx RAx A9 A0-A9 RAx RBx CAx DQM Hi-Z DAx0 DAx1 DAx2 DAx3 ...

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... IS42S32800B Figure 18.2.Full Page Read Cycle (Burst Length=Full Page,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 High CKE CS# RAS# CAS# WE# BS0,1 RBx RAx A10 A0-A9 RAx CAx RBx DQM Hi Read Activate Activate Command ...

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... IS42S32800B Figure 18.3.Full Page Read Cycle (Burst Length=Full Page,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 High CKE CS# RAS# CAS# WE# BS0,1 RAx A10 A0-A9 RAx CAx DQM DQ Hi-Z Activate Read Command Command Bank A ...

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... IS42S32800B Figure 19.2.Full Page Write Cycle (Burst Length=Full Page,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 High CKE CS# RAS# CAS# WE# BS0,1 RAx RBx A10 A0-A9 RAx CAx DQM Hi-Z DQ DAx DAx+1 DAx+2 DAx+3 DAx-1 ...

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... IS42S32800B Figure 19.3.Full Page Write Cycle (Burst Length=Full Page,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE High CS# RAS# CAS# WE# BS0,1 RAx A10 RAx CAx A0-A9 DQM Hi-Z DQ DAx DAx+1 DAx+2 DAx+3 DAx-1 DAx ...

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... IS42S32800B Figure 20.Byte Write Operation (Burst Length=4,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 High CKE CS# RAS# CAS# WE# BS0,1 RAx A10 A0-A9 RAx CAx DQM0 DQM1,2,3 DQ0 - DQ7 DQ8 - DQ15 Read Activate Command ...

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... IS42S32800B Figure 22.Full Page Random Column Read (Burst Length=Full Page,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T2 2 CLK t CK2 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx RBx RAx RBx CAx CBx CAy A0-A9 DQM t t RRD ...

Page 57

... IS42S32800B Figure 23.Full Page Random Column Write (Burst Length=Full Page,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS# RAS# CAS# WE# BS0,1 RAx RBx A10 A0-A9 RAx RBx CAx DQM t t RRD RCD DQ DAx0 DBx0 DAy0 DAy1 DBy0 DBy1 DAz0 DAz1 DAz2 DBz0 ...

Page 58

... IS42S32800B Figure 24.2.Precharge Termination of a Burst (Burst Length=8 or Full Page,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE High CS# RAS# CAS# WE# BS0,1 RAx A10 RAx CAx A0-A9 DQM DQ DAx0 DAx1 DAx2 DAx3 Write ...

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... IS42S32800B Figure 24.3.Precharge Termination of a Burst (Burst Length=4,8 or Full Page,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 High CKE CS# RAS# CAS# WE# BS0,1 RAx A10 RAx CAx A0-A9 DQM DQ DAx0 DAx1 Write Activate Command ...

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... Order Part No. Package IS42S32800B-6TI 400 mil TSOP-II IS42S32800B-6TLI 400 mil TSOP-II, Lead-free IS42S32800B-6BI 8 x13mm BGA IS42S32800B-6BLI 8 x13mm BGA, Lead-free IS42S32800B-7TI 400 mil TSOP-II IS42S32800B-7TLI 400 mil TSOP-II, Lead-free IS42S32800B-7BI 8 x13mm BGA IS42S32800B-7BLI 8 x13mm BGA, Lead-free Integrated Silicon Solution, Inc. Rev. F 07/21/09 ...

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... IS42S32800B Integrated Silicon Solution, Inc. Rev. F 07/21/09 61 ...

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... IS42S32800B 62 D1 Integrated Silicon Solution, Inc. Rev. F 07/21/09 ...

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