IS61NLP51236-200TQLI INTEGRATED SILICON SOLUTION (ISSI), IS61NLP51236-200TQLI Datasheet

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IS61NLP51236-200TQLI

Manufacturer Part Number
IS61NLP51236-200TQLI
Description
IC, SRAM, 18MBIT, 3.1NS, TQFP-100
Manufacturer
INTEGRATED SILICON SOLUTION (ISSI)
Datasheet

Specifications of IS61NLP51236-200TQLI

Memory Size
18Mbit
Memory Configuration
512K X 36
Clock Frequency
200MHz
Access Time
3.1ns
Supply Voltage Range
3V To 3.6V
Memory Case Style
TQFP
No. Of Pins
100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
IS61NLP51236/IS61NVP51236
IS61NLP102418/IS61NVP102418 
256K x 72, 512K x 36 and 1M x 18
18Mb, PIPELINE 'NO WAIT' STATE BUS SRAM
FEATURES
• 100 percent bus utilization
• No wait cycles between Read and Write
• Internal self-timed write cycle
• Individual Byte Write Control
• Single R/W (Read/Write) control pin
• Clock controlled, registered address,
• Interleaved or linear burst sequence control us-
• Three chip enables for simple depth expansion
• Power Down mode
• Common data inputs and data outputs
• CKE pin to enable clock and suspend operation
• JEDEC 100-pin TQFP, 165-ball PBGA and 209-
• Power supply:
• JTAG Boundary Scan for PBGA packages
• Industrial temperature available
• Lead-free available
FAST ACCESS TIME
Symbol 
t
t
Integrated Silicon Solution, Inc. — www.issi.com
Rev.  M
01/06/2011
Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
data and control
ing MODE input
and address pipelining
ball (x72) PBGA packages
NVP: V
NLP: V
kq
kc
dd
dd
3.3V (± 5%), V
2.5V (± 5%), V
Parameter 
Clock Access Time
Cycle Time
Frequency
ddq
ddq
3.3V/2.5V (± 5%)
2.5V (± 5%)
-250 
250
2.6
4
DESCRIPTION
The 18 Meg 'NLP/NVP' product family feature high-speed,
low-power synchronous static RAMs designed to provide
a burstable, high-performance, 'no wait' state, device
for networking and communications applications. They
are organized as 256K words by 72 bits, 512K words
by 36 bits and 1M words by 18 bits, fabricated with
advanced CMOS technology.
Incorporating a 'no wait' state feature, wait cycles are
eliminated when the bus switches from read to write, or
write to read. This device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit.
All synchronous inputs pass through registers are controlled
by a positive-edge-triggered single clock input. Operations
may be suspended and all synchronous inputs ignored
when Clock Enable, CKE is HIGH. In this state the internal
device will hold their previous values.
All Read, W rite and Deselect cycles are initiated by the ADV
input. When the ADV is HIGH the internal burst counter
is incremented. New external addresses can be loaded
when ADV is LOW.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock inputs and when WE is LOW.
Separate byte enables allow individual bytes to be written.
A burst mode pin (MODE) defines the order of the burst
sequence. W hen tied HIGH, the interleaved burst sequence
is selected. When tied LOW, the linear burst sequence is
selected.
-200 
200
3.1
5
Units
MHz
ns
ns
JANUARY 2011
ISSI
's
1

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IS61NLP51236-200TQLI Summary of contents

Page 1

... IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418  256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE 'NO WAIT' STATE BUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control us- ing MODE input • ...

Page 2

... IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418    BLOCK DIAGRAM x 72: A [0:17 36: A [0:18] or ADDRESS x 18: A [0:19] REGISTER CLK CONTROL LOGIC K CKE CE CE2 CE2 CONTROL } ADV REGISTER WE BWŸ X (X=a,b,c DQx/DQPx 2 A2-A17 or A2-A18 or A2-A19 MODE BURST ADDRESS A0-A1 A'0-A'1 COUNTER WRITE WRITE ...

Page 3

... IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418    Bottom View 209-Ball BGA 1 mm Ball Pitch Ball Array Integrated Silicon Solution, Inc. — www.issi.com Rev.  M 01/06/2011 Bottom View 165-Ball 15mm BGA 1 mm Ball Pitch Ball Array 3 ...

Page 4

... IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418    PIN CONFIgURATION   —  256K x 72, 209-Ball PBgA (TOP VIEW DQg DQg A B DQg DQg BWc C DQg DQg BWh D DQg DQg DQPg DQPc V ddq F DQc DQc DQc DQc V ddq H DQc DQc V SS ...

Page 5

... IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418    PIN CONFIgURATION   —  512K  CE2 C DQPc NC V ddq D DQc DQc V ddq E DQc DQc V ddq F DQc DQc V ddq G DQc DQc V ddq H NC VDD NC J DQd DQd V ddq K DQd DQd V ddq L DQd DQd V ddq ...

Page 6

... IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418    165-PIN PBgA PACKAgE CONFIGURATION       1024K x 18 (TOP VIEW)  CE2 DDQ DQb DDQ V DQb E NC DDQ DQb DDQ V DDQ G NC DQb DDQ DQb DQb DDQ DQb DDQ ...

Page 7

... IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418    PIN CONFIGURATION 100-Pin TQFP 100 DQPc 1 2 DQc 3 DQc 4 V DDQ 5 Vss 6 DQc 7 DQc 8 DQc 9 DQc 10 Vss 11 V DDQ 12 DQc 13 DQc Vss 18 DQd 19 DQd 20 V DDQ 21 Vss DQd 22 23 DQd 24 DQd DQd 25 Vss DDQ DQd ...

Page 8

... IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418    STATE DIAGRAM BEGIN READ READ READ BURST BURST BURST READ SYNCHRONOUS TRUTH TABLE   Address  Operation  Used  Not Selected N/A Not Selected N/A Not Selected N/A Not Selected Continue N/A Begin Burst Read External Address Continue Burst Read Next Address NOP/Dummy Read External Address Dummy Read ...

Page 9

... IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418    ASYNCHRONOUS TRUTH TABLE Operation  ZZ  Sleep Mode H Read L L Write L Deselected L Notes means "Don't Care". 2. For write cycles following read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur. 3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle time. 4. Deselected means power Sleep Mode where stand-by current depends on cycle time. WRITE TRUTH TABLE  (x18) Operation  WE READ H WRITE BYTE a L WRITE BYTE b L WRITE ALL BYTEs ...

Page 10

... IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418    WRITE TRUTH TABLE  (x72) Operation  WE READ H WRITE BYTE a L WRITE BYTE b L WRITE BYTE c L WRITE BYTE d L WRITE BYTE e L WRITE BYTE f L WRITE BYTE g L WRITE BYTE h L WRITE ALL BYTEs L WRITE ABORT/NOP L Notes means "Don't Care". 2. All inputs in this table must beet setup and hold time around the rising edge of CLK. INTERLEAVED BURST ADDRESS TABLE  ...

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... IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418    LINEAR BURST ADDRESS TABLE  A1', A0' = 1,1 ABSOLUTE MAxIMUM RATINgS   Symbol  Parameter  T Storage Temperature STG P Power Dissipation d I Output Current (per I/O) ouT Voltage Relative ouT V Voltage Relative for Address and Control Inputs Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied ...

Page 12

... IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418    DC ELECTRICAL CHARACTERISTICS      Symbol  Parameter  Test Conditions    V Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Ih V Input LOW Voltage Il I Input Leakage Current Output Leakage Current V lo POWER SUPPLY CHARACTERISTICS       Symbol  Parameter  ...

Page 13

... IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418    CAPACITANCE (1,2)   Symbol  Parameter    c Input Capacitance In c Input/Output Capacitance ouT Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions 25° MHz 3.3V I/O AC TEST CONDITIONS   Parameter    Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load See Figures 1 and 2 3.3V I/O OUTPUT LOAD EQUIVALENT Zo= 50Ω ...

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... IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418    2.5V I/O AC TEST CONDITIONS   Parameter    Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load See Figures 3 and 4 2.5V I/O OUTPUT LOAD EQUIVALENT Z = 50Ω O OUTPUT Figure 3 14 Unit 0V to 2.5V 1.5 ns 1.25V OUTPUT 50Ω 1.25V Integrated Silicon Solution, Inc. — www.issi.com 1,667 Ω ...

Page 15

... IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418    READ/WRITE CYCLE SWITCHINg CHARACTERISTICS         Symbol  Parameter  fmax Clock Frequency t Cycle Time kc t Clock High Time kh t Clock Low Time kl t Clock Access Time kq t Clock High to Output Invalid (2) kqx t Clock High to Output Low-Z (2,3) kqlZ t Clock High to Output High-Z (2,3) kqhZ t Output Enable to Output Valid ...

Page 16

... IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418    SLEEP MODE ELECTRICAL CHARACTERISTICS   Symbol  Parameter    I Current during SLEEP MODE ZZ active to input ignored PdS t ZZ inactive to input sampled PuS t ZZ active to SLEEP current ZZI t ZZ inactive to exit SLEEP current rZZI SLEEP MODE TIMINg CLK t PDS ZZ setup cycle ZZ t ZZI Isupply I SB2 All Inputs ...

Page 17

... IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418    READ CYCLE TIMINg CLK t t ADVS ADVH ADV Address WRITE CKE t t CES CEH OEQ t OEHZ Data Out Q1-1 NOTES: WRITE = L means and BWx = and BWX = means CE1 = L, CE2 = H and CE2 = means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L Integrated Silicon Solution, Inc. — ...

Page 18

... IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418    WRITE CYCLE TIMINg t KH CLK t KC ADV Address A1 A2 WRITE CKE CE OE Data In D1-1 t OEHZ Data Out Q0-3 Q0-4 NOTES: WRITE = L means and BWx = and BWX = means CE1 = L, CE2 = H and CE2 = means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L ...

Page 19

... IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418    SINgLE READ/WRITE CYCLE TIMINg CLK CKE Address WRITE CE ADV OE t OEQ t OELZ Data Out Q1 Data In NOTES: WRITE = L means and BWx = means CE1 = L, CE2 = H and CE2 = means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L Integrated Silicon Solution, Inc. — ...

Page 20

... IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418    CKE  OPERATION TIMINg CLK CKE Address A1 A2 WRITE CE ADV OE Data Out Data In NOTES: WRITE = L means and BWx = means CE1 = L, CE2 = H and CE2 = means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = KQHZ t KQLZ Q1 Integrated Silicon Solution, Inc. — www.issi.com ...

Page 21

... IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418    CE OPERATION TIMINg CLK CKE A1 A2 Address WRITE CE ADV OE t OEQ t OELZ Q1 Data Out Data In NOTES: WRITE = L means and BWx = means CE1 = L, CE2 = H and CE2 = means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L Integrated Silicon Solution, Inc. — www.issi.com Rev.  ...

Page 22

... IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418    IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAg) The IS61NLP and IS61NVP have a serial boundary scan Test Access Port (TAP) in the PBGA package only. (Not available in TQFP package.) This port operates in ac- cordance with IEEE Standard 1149.1-1900, but does not include all functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because they place added delay in the critical speed path of the SRAM. The TAP controller operates in a manner that does not conflict with the performance of other devices us- ing 1149.1 fully compliant TAPs. The TAP operates using JEDEC standard 2.5V I/O logic levels. ...

Page 23

... IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418    TEST DATA OUT (TDO) The TDO output pin is used to serially clock data-out from the registers. The output is active depending on the current state of the TAP state machine (see TAP Controller State Diagram). The output changes on the falling edge of TCK and TDO is connected to the Least Significant Bit (LSB) of any register. PERFORMINg A TAP RESET A Reset is performed by forcing TMS HIGH (V rising edges of TCK. RESET may be performed while the SRAM is operating and does not affect its operation ...

Page 24

... IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418    TAP INSTRUCTION SET Eight instructions are possible with the three-bit instruction register and all combinations are listed in the Instruction Code table. Three instructions are listed as RESERVED and should not be used and the other five instructions are described below. The TAP controller used in this SRAM is not fully compliant with the 1149.1 convention because some mandatory instructions are not fully implemented. The TAP controller cannot be used to load address, data or control signals and cannot preload the Input or Output buf- fers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/ PRELOAD; instead it performs a capture of the Inputs and Output ring when these instructions are executed ...

Page 25

... IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418    INSTRUCTION CODES  Code  Instruction  Description 000 EXTEST Captures the Input/Output ring contents. Places the boundary scan register be- tween the TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant. 001 IDCODE Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. 010 SAMPLE-Z Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. 011 RESERVED Do Not Use: This instruction is reserved for future use. ...

Page 26

... IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418    TAP Electrical Characteristics Over the Operating Range Symbol  Parameter  V Output HIGH Voltage oh1 V Output HIGH Voltage oh2 V Output LOW Voltage ol1 V Output LOW Voltage ol2 V Input HIGH Voltage Ih V Input LOW Voltage Il I Input Leakage Current x Notes: 1. All Voltage referenced to Ground. 2. Overshoot: V (AC) ≤ V +1.5V for ≤ ≤ Undershoot: V (AC) 0.5V for t Il Power-up: V < ...

Page 27

... IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418    TAP AC TEST CONDITIONS (2.5V/3.3V) Input pulse levels 0 to 2.5V/0 to 3.0V Input rise and fall times Input timing reference levels Output reference levels Test load termination supply voltage Vtrig TAP TIMINg 1 t THTH TCK t MVTH TMS t DVTH TDI TDO Integrated Silicon Solution, Inc. — www.issi.com Rev.  M 01/06/2011 TAP Output Load Equivalent 1ns 1 ...

Page 28

... IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418    209 BOUNDARY SCAN ORDER (256K x 72) 28 Integrated Silicon Solution, Inc. — www.issi.com Rev.  M 01/06/2011 ...

Page 29

... IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418    165 PBgA BOUNDARY SCAN ORDER (x 36) Signal  Bump    B it #  Name  ID  Bit #  1 MODE 11P 10P 10R 11R 11H 31 12 DQa 11N 32 13 DQa 11M 33 14 DQa ...

Page 30

... IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418    165 PBgA BOUNDARY SCAN ORDER (x 18) Signal  Bump    B it #  Name  ID  Bit #  1 MODE 11P 10P 10R 11R 11H 11N 11M 11L 11K 11J 36 17 DQa 10M ...

Page 31

... Order Part Number  Package IS61NLP25672-250B1I 209 PBGA IS61NLP25672-200B1I 209 PBGA IS61NLP25672-200B1LI 209 PBGA, Lead-free IS61NLP51236-250TQI 100 TQFP IS61NLP51236-250TQLI 100 TQFP, Lead-free IS61NLP51236-250B3I 165 PBGA IS61NLP51236-200TQI 100 TQFP IS61NLP51236-200TQLI 100 TQFP, Lead-free IS61NLP51236-200B3I 165 PBGA IS61NLP51236-200B3LI 165 PBGA, Lead-free IS61NLP102418-250TQI 100 TQFP IS61NLP102418-250B3I 165 PBGA IS61NLP102418-200TQI 100 TQFP IS61NLP102418-200TQLI 100 TQFP, Lead-free IS61NLP102418-200B3I 165 PBGA IS61NLP102418-200B3LI ...

Page 32

... IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418    ORDERINg INFORMATION (2.5V core/2.5V I/O) Commercial Range: 0°C to +70°C   Configuration  Access Time    256Kx72 250 200   512Kx36 250 200   1Mx18 250 200 Industrial Range: -40°C to +85°C   ...

Page 33

... IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418    Integrated Silicon Solution, Inc. — www.issi.com Rev.  M 01/06/2011 33 ...

Page 34

... IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418    34 Integrated Silicon Solution, Inc. — www.issi.com Rev.  M 01/06/2011 ...

Page 35

... IS61NLP25672/IS61NVP25672  IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418    Integrated Silicon Solution, Inc. — www.issi.com Rev.  M 01/06/2011 35 ...

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