LPC2468FBD208 NXP Semiconductors, LPC2468FBD208 Datasheet - Page 34

IC, 32BIT MCU, ARM7, 72MHZ, LQFP-208

LPC2468FBD208

Manufacturer Part Number
LPC2468FBD208
Description
IC, 32BIT MCU, ARM7, 72MHZ, LQFP-208
Manufacturer
NXP Semiconductors
Datasheet

Specifications of LPC2468FBD208

Controller Family/series
(ARM7)
No. Of I/o's
160
Ram Memory Size
98KB
Cpu Speed
72MHz
No. Of Timers
4
No. Of Pwm Channels
12
Core Size
32 Bit
Program Memory Size
512KB
Rohs Compliant
Yes
Oscillator Type
External, Internal
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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NXP Semiconductors
LPC2468
Product data sheet
7.13.1 Features
7.14.1 Features
7.15.1 Features
7.13 10-bit ADC
7.14 10-bit DAC
7.15 UARTs
The LPC2468 contains one ADC. It is a single 10-bit successive approximation ADC with
eight channels.
The DAC allows the LPC2468 to generate a variable analog output. The maximum output
value of the DAC is V
The LPC2468 contains four UARTs. In addition to standard transmit and receive data
lines, UART1 also provides a full modem control handshake interface.
The UARTs include a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
Acceptance Filter can provide Full CAN-style automatic reception for selected
Standard Identifiers.
FullCAN messages can generate interrupts.
10-bit successive approximation ADC
Input multiplexing among 8 pins
Power-down mode
Measurement range 0 V to V
10-bit conversion time ≥ 2.44 μs
Burst conversion mode for single or multiple inputs
Optional conversion on transition of input pin or Timer Match signal
Individual result registers for each ADC channel to reduce interrupt overhead
10-bit DAC
Resistor string architecture
Buffered output
Power-down mode
Selectable output drive
16 B Receive and Transmit FIFOs.
Register locations conform to 16C550 industry standard.
Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
All information provided in this document is subject to legal disclaimers.
i(VREF)
Rev. 5 — 15 October 2010
.
i(VREF)
Single-chip 16-bit/32-bit micro
LPC2468
© NXP B.V. 2010. All rights reserved.
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