PIC16F1827-I/MQ Microchip Technology, PIC16F1827-I/MQ Datasheet - Page 256

• Manufacturer Part Number: PIC16F1827-I/MQ
• Description: IC, 8BIT MCU, PIC16F, 32MHZ, QFN-28
• Manufacturer: Microchip Technology

Specifications of PIC16F1827-I/MQ

• Controller Family/series: PIC16F
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 384Byte
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Interface: EUSART, I2C, SPI
• Core Size: 8 Bit
• Program Memory Size: 4 Kwords
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Data Ram Size: 384 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN EP
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / Rohs Status: Details

PIC16F/LF1826/27
24.5.3.3
Setting the AHEN bit of the SSPxCON3 register
enables additional clock stretching and interrupt gen-
eration after the 8th falling edge of a received match-
ing address. Once a matching address has been
clocked in, CKP is cleared and the SSPxIF interrupt is
set.
Figure 24-18 displays a standard waveform of a 7-bit
Address Slave Transmission with AHEN enabled.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Slave hardware automatically clears the CKP bit
11. Slave software clears SSPxIF.
12. Slave loads value to transmit to the master into
13. Slave sets CKP bit releasing the clock.
14. Master clocks out the data from the slave and
15. Slave hardware copies the ACK value into the
16. Steps 10-15 are repeated for each byte transmit-
17. If the master sends a not ACK the slave
DS41391B-page 256
Note: SSPxBUF cannot be loaded until after the
Note: Master must send a not ACK on the last byte
Bus starts Idle.
Master sends Start condition; the S bit of SSPx-
STAT is set; SSPxIF is set if interrupt on Start
detect is enabled.
Master sends matching address with R/W bit
set. After the 8th falling edge of the SCLx line the
CKP bit is cleared and SSPxIF interrupt is gen-
erated.
Slave software clears SSPxIF.
Slave software reads ACKTIM bit of SSPxCON3
register, and R/W and D/A of the SSPxSTAT
register to determine the source of the interrupt.
Slave reads the address value from the SSPx-
BUF register clearing the BF bit.
Slave software decides from this information if it
wishes to ACK or not ACK and sets ACKDT bit
of the SSPxCON2 register accordingly.
Slave sets the CKP bit releasing SCLx.
Master clocks in the ACK value from the slave.
and sets SSPxIF after the ACK if the R/W bit is
set.
SSPxBUF setting the BF bit.
sends an ACK value on the 9th SCLx pulse.
ACKSTAT bit of the SSPxCON2 register.
ted to the master from the slave.
releases the bus allowing the master to send a
Stop and end the communication.
ACK.
to ensure that the slave releases the SCLx
line to receive a Stop.
7-bit Transmission with Address
Hold Enabled
Preliminary
© 2009 Microchip Technology Inc.