LPC2119FBD64 NXP Semiconductors, LPC2119FBD64 Datasheet
LPC2119FBD64
Specifications of LPC2119FBD64
Available stocks
Related parts for LPC2119FBD64
LPC2119FBD64 Summary of contents
Page 1
LPC2109/2119/2129 Single-chip 16/32-bit microcontrollers; 64/128/256 kB ISP/IAP flash with 10-bit ADC and CAN Rev. 06 — 10 December 2007 1. General description The LPC2109/2119/2129 are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, together with ...
Page 2
... CPU operating voltage range of 1. 1. I/O power supply range of 3 3 Ordering information Table 1. Type number LPC2109FBD64/00 LPC2109FBD64/01 LPC2119FBD64 LPC2119FBD64/00 LPC2119FBD64/01 LPC2109_2119_2129_6 Product data sheet Ordering information Package Name Description LQFP64 plastic low profile quad flat package; 64 leads; body 10 LQFP64 plastic low profi ...
Page 3
... Table 1. Type number LPC2129FBD64 LPC2129FBD64/00 LPC2129FBD64/01 3.1 Ordering options Table 2. Type number LPC2109FBD64/ LPC2109FBD64/ LPC2119FBD64 LPC2119FBD64/00 128 kB LPC2119FBD64/01 128 kB LPC2129FBD64 LPC2129FBD64/00 256 kB LPC2129FBD64/01 256 kB LPC2109_2119_2129_6 Product data sheet Ordering information …continued Package Name Description LQFP64 plastic low profile quad flat package; 64 leads; ...
Page 4
... NXP Semiconductors 4. Block diagram LPC2109 LPC2119 LPC2129 P0[30:27], HIGH-SPEED P0[25:0] (4) GPI/O 46 PINS TOTAL P1[31:16] ARM7 LOCAL BUS INTERNAL SRAM CONTROLLER 8/16 kB SRAM EXTERNAL (1) EINT[3:0] INTERRUPTS (1) 4 CAP0 CAPTURE/ (1) 4 CAP1 COMPARE (1) 4 MAT0 TIMER 0/TIMER 1 (1) 4 MAT1 (1) AIN[3:0] A/D CONVERTER P0[30:27], ...
Page 5
... NXP Semiconductors 5. Pinning information 5.1 Pinning P0[21]/PWM5/CAP1[3] 1 P0[22]/CAP0[0]/MAT0[0] 2 (1) 3 P0[23]/RD2 P1[19]/TRACEPKT3 4 (1) P0[24]/TD2 DDA(3V3) P1[18]/TRACEPKT2 8 P0[25]/RD1 9 10 TD1 P0[27]/AIN0/CAP0[1]/MAT0[1] 11 P1[17]/TRACEPKT1 12 P0[28]/AIN1/CAP0[2]/MAT0[ P0[29]/AIN2/CAP0[3]/MAT0[3] P0[30]/AIN3/EINT3/CAP0[0] 15 P1[16]/TRACEPKT0 16 (1) No TD2 and RD2 for LPC2109 ...
Page 6
... NXP Semiconductors 5.2 Pin description Table 3. Pin description Symbol Pin P0[0] to P0[31] P0[0]/TXD0/ 19 PWM1 P0[1]/RXD0/ 21 PWM3/EINT0 P0[2]/SCL/ 22 CAP0[0] P0[3]/SDA/ 26 MAT0[0]/EINT1 P0[4]/SCK0/ 27 CAP0[1] P0[5]/MISO0/ 29 MAT0[1] P0[6]/MOSI0/ 30 CAP0[2] P0[7]/SSEL0/ 31 PWM2/EINT2 P0[8]/TXD1/ 33 PWM4 P0[9]/RXD1/ ...
Page 7
... NXP Semiconductors Table 3. Pin description …continued Symbol Pin P0[15]/RI1/EINT2 45 P0[16]/EINT0/ 46 MAT0[2]/CAP0[2] P0[17]/CAP1[2]/ 47 SCK1/MAT1[2] P0[18]/CAP1[3]/ 53 MISO1/MAT1[3] P0[19]/MAT1[2]/ 54 MOSI1/CAP1[2] P0[20]/MAT1[3]/ 55 SSEL1/EINT3 P0[21]/PWM5/ 1 CAP1[3] P0[22]/CAP0[0]/ 2 MAT0[0] P0[23]/RD2 3 P0[24]/TD2 5 P0[25]/RD1 9 P0[27]/AIN0/ 11 CAP0[1]/MAT0[1] ...
Page 8
... NXP Semiconductors Table 3. Pin description …continued Symbol Pin P1[16]/ 16 TRACEPKT0 P1[17]/ 12 TRACEPKT1 P1[18]/ 8 TRACEPKT2 P1[19]/ 4 TRACEPKT3 P1[20]/ 48 TRACESYNC P1[21]/ 44 PIPESTAT0 P1[22]/ 40 PIPESTAT1 P1[23]/ 36 PIPESTAT2 P1[24]/ 32 TRACECLK P1[25]/EXTIN0 28 P1[26]/RTCK 24 P1[27]/TDO 64 P1[28]/TDI 60 P1[29]/TCK 56 P1[30]/TMS 52 P1[31]/TRST 20 TD1 ...
Page 9
... NXP Semiconductors Table 3. Pin description …continued Symbol Pin V 63 DDA(1V8) V 23, 43, 51 DD(3V3 DDA(3V3) [1] SSP interface available on LPC2109/01, LPC2119/01, and LPC2129/01 only. LPC2109_2119_2129_6 Product data sheet Type Description I Analog 1.8 V core power supply; this is the power supply voltage for internal circuitry. This should be nominally the same voltage as V isolated to minimize noise and error ...
Page 10
... NXP Semiconductors 6. Functional description Details of the LPC2109/2119/2129 systems and peripheral functions are described in the following sections. 6.1 Architectural overview The ARM7TDMI general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers ...
Page 11
... NXP Semiconductors However, the ISP flash erase command can be executed at any time (no matter whether the CRP off). Removal of CRP is achieved by erasure of full on-chip user flash. With the CRP off, full access to the chip via the JTAG and/or ISP is restored. 6.3 On-chip static RAM On-chip static RAM may be used for code and/or data storage ...
Page 12
... NXP Semiconductors Fig 3. LPC2109/2119/2129 memory map 6.5 Interrupt controller The Vectored Interrupt Controller (VIC) accepts all of the interrupt request inputs and categorizes them as Fast Interrupt reQuest (FIQ), vectored Interrupt Request (IRQ), and non-vectored IRQ as defined by programmable settings. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted ...
Page 13
... NXP Semiconductors Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned to this category. Any of the interrupt requests can be assigned to any of the 16 vectored IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest. Non-vectored IRQs have the lowest priority. ...
Page 14
... NXP Semiconductors Table 4. Block System Control ADC CAN [1] SSP interface available on LPC2109/01, LPC2119/01, and LPC2129/01 only. 6.6 Pin connect block The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals ...
Page 15
... NXP Semiconductors 6.8 10-bit ADC The LPC2109/2119/2129 each contain a single 10-bit successive approximation ADC with four multiplexed channels. 6.8.1 Features • Measurement range • Capable of performing more than 400000 10-bit samples per second. • Burst conversion mode for single or multiple inputs. ...
Page 16
... NXP Semiconductors • UART1 is equipped with standard modem interface signals. This module also provides full support for hardware flow control (auto-CTS/RTS). 6.10.2 UART features available in LPC2109/2119/2129/01 only Compared to previous LPC2000 microcontrollers, UARTs in LPC2109/2119/2129/01 introduce a fractional baud rate generator for both UARTs, enabling these microcontrollers to achieve standard baud rates such as 115200 Bd with any crystal frequency above 2 MHz. In addition, auto-CTS/RTS fl ...
Page 17
... NXP Semiconductors 6.12 SPI serial I/O controller The LPC2109/2119/2129 each contain two SPIs. The SPI is a full duplex serial interface, designed to be able to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer ...
Page 18
... NXP Semiconductors to trap the timer value when an input signal transitions, optionally generating an interrupt. Multiple pins can be selected to perform a single capture or match function, providing an application with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them. 6.14.1 Features • A 32-bit Timer/Counter with a programmable 32-bit Prescaler. ...
Page 19
... NXP Semiconductors • Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. • Incorrect/incomplete feed sequence causes reset/interrupt if enabled. • Flag to indicate watchdog reset. • Programmable 32-bit timer with internal pre-scaler. • Selectable time period from (T T cy(PCLK) 6.16 Real-time clock The RTC is designed to provide a set of counters to measure time when normal or idle operating mode is selected ...
Page 20
... NXP Semiconductors Three match registers can be used to provide a PWM output with both edges controlled. Again, the MR0 match register controls the PWM cycle rate. The other match registers control the two PWM edge positions. Additional double edge controlled PWM outputs require only two match registers each, since the repetition rate is the same for all PWM outputs. With double edge controlled PWM outputs, specifi ...
Page 21
... NXP Semiconductors 6.18.2 PLL The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from (in practice, the multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper frequency limit of the CPU) ...
Page 22
... NXP Semiconductors CRP1 disables access to chip via the JTAG and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased. ...
Page 23
... NXP Semiconductors 6.18.8 APB The APB divider determines the relationship between the processor clock (CCLK) and the clock used by peripheral devices (PCLK). The APB divider serves two purposes. The first is to provide peripherals with the desired PCLK via APB so that they can operate at the speed chosen for the ARM processor ...
Page 24
... NXP Semiconductors pipeline status on a cycle by cycle basis. Trace information generation can be controlled by selecting the trigger resource. Trigger resources include address comparators, counters and sequencers. Since trace information is compressed the software debugger requires a static image of the code being executed. Self-modifying code can not be traced because of this restriction ...
Page 25
... NXP Semiconductors 7. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (1.8 V) DD(1V8) V supply voltage (3.3 V) DD(3V3) V analog supply voltage (3.3 V) DDA(3V3) V analog input voltage IA V input voltage I I supply current DD I ground current ...
Page 26
... NXP Semiconductors 8. Static characteristics Table 6. Static characteristics +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter V supply voltage (1.8 V) DD(1V8) V supply voltage (3.3 V) DD(3V3) V analog supply voltage DDA(3V3) (3.3 V) Standard port pins, RESET, RTCK I LOW-level input current IL I HIGH-level input current ...
Page 27
... NXP Semiconductors Table 6. Static characteristics +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter Power consumption LPC2109/01, LPC2119/01, LPC2129/01 I active mode supply DD(act) current I Idle mode supply current DD(idle) I Power-down mode supply DD(pd) current 2 I C-bus pins V HIGH-level input voltage ...
Page 28
... NXP Semiconductors Table 7. ADC static characteristics 3.6 V unless otherwise specified; T DDA 4.5 MHz. Symbol Parameter V analog input voltage IA C analog input ia capacitance E differential linearity D error E integral non-linearity L(adj) E offset error O E gain error G E absolute error T [1] Conditions 3.3 V. ...
Page 29
... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. Fig 4. ADC characteristics LPC2109_2119_2129_6 Product data sheet ...
Page 30
... NXP Semiconductors 8.1 Power consumption measurements for LPC2109/01, LPC2119/01, LPC2129/01 devices The power consumption measurements represent typical values for the given conditions. The peripherals were enabled through the PCONP register, but for these measurements, the peripherals were not configured to run. Peripherals were disabled through the PCONP register ...
Page 31
... NXP Semiconductors 10 I DD(idle) (mA Test conditions: Idle mode entered executing code from on-chip flash; PCLK = core voltage 1.8 V. amb Fig 7. Typical LPC2109/01 I DD(idle DD(idle) (mA) 7.5 5.0 2.5 0 1.65 1.70 Test conditions: Idle mode entered executing code from on-chip flash; PCLK = core voltage 1.8 V; all peripherals enabled. ...
Page 32
... NXP Semiconductors 45 I DD(act) (mA Test conditions: Active mode entered executing code from on-chip flash; PCLK = core voltage 1.8 V. amb Fig 9. Typical LPC2119/01 and LPC2129/ DD(act) (mA 1.65 1.70 Test conditions: Active mode entered executing code from on-chip flash; PCLK = core voltage 1.8 V; all peripherals enabled. ...
Page 33
... NXP Semiconductors 10 I DD(idle) (mA Test conditions: Idle mode entered executing code from on-chip flash; PCLK = core voltage 1.8 V. amb Fig 11. Typical LPC2119/01 and LPC2129/ DD(idle) (mA 1.65 1.70 Test conditions: Idle mode entered executing code from on-chip flash; PCLK = core voltage 1.8 V; all peripherals enabled. ...
Page 34
... NXP Semiconductors 45 I DD(act) (mA 1.65 1.70 Test conditions: Active mode entered executing code from on-chip flash; PCLK = Temp = 25 C; core voltage 1.8 V; all peripherals disabled. Fig 13. Typical LPC2109/01, LPC2119/01, and LPC2129/ DD(idle) (mA 1.65 1.70 Test conditions: Idle mode entered executing code from on-chip flash; PCLK = Temp = 25 C ...
Page 35
... NXP Semiconductors 45 I DD(act) (mA Test conditions: Active mode entered executing code from on-chip flash; PCLK = core voltage 1.8 V; all peripherals disabled. Fig 15. Typical LPC2109/01, LPC2119/01, and LPC2129/ DD(idle) (mA Test conditions: Idle mode entered executing code from on-chip flash; PCLK = core voltage 1.8 V; all peripherals disabled. ...
Page 36
... NXP Semiconductors 200 I DD(pd 160 120 Test conditions: Power-down mode entered executing code from on-chip flash. Fig 17. Typical LPC2109/01, LPC2119/01, and LPC2129/01 core power-down current I temperatures Table 8. Core voltage 1 Peripheral Timer0 Timer1 UART0 UART1 PWM0 2 I C-bus SPI0/1 RTC ADC CAN1 Table 9. Core voltage 1.8 V ...
Page 37
... NXP Semiconductors Table 9. Core voltage 1 Peripheral RTC ADC CAN1/2 LPC2109_2119_2129_6 Product data sheet Typical LPC2119/01 and LPC2129/01 peripheral power consumption in active mode …continued = 25 C; all measurements in A; PCLK = amb CCLK = 12 MHz 16 33 229 Rev. 06 — 10 December 2007 LPC2109/2119/2129 Single-chip 16/32-bit microcontrollers CCLK ...
Page 38
... NXP Semiconductors 9. Dynamic characteristics Table 10. Dynamic characteristics +85 C for industrial applications; V amb Symbol Parameter External clock f oscillator frequency osc T clock cycle time cy(clk) t clock HIGH time CHCX t clock LOW time CLCX t clock rise time CLCH t clock fall time CHCL Port pins (except P0[2] and P0[3]) ...
Page 39
... NXP Semiconductors 9.1 Timing V Fig 18. External clock timing LPC2109_2119_2129_6 Product data sheet 0 0.2V 0 0. CHCL Rev. 06 — 10 December 2007 LPC2109/2119/2129 Single-chip 16/32-bit microcontrollers t CHCX t t CLCX CLCH T cy(clk) 002aaa907 © NXP B.V. 2007. All rights reserved ...
Page 40
... NXP Semiconductors 10. Package outline LQFP64: plastic low profile quad flat package; 64 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 mm 1.6 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION ...
Page 41
... NXP Semiconductors 11. Abbreviations Table 11. Acronym ADC AMBA APB CAN CPU DCC FIFO GPIO I/O PLL PWM RAM SPI SRAM SSI SSP TTL UART LPC2109_2119_2129_6 Product data sheet Abbreviations Description Analog-to-Digital Converter Advanced Microcontroller Bus Architecture Advanced Peripheral Bus Controller Area Network ...
Page 42
... Modifications: Type number LPC2109FBD64/01 has been added. • Type number LPC2119FBD64/01 has been added. • Type number LPC2129FBD64/01 has been added. • Details introduced with /01 devices on new peripherals/features (Fast I/O Ports, SSP, CRP) and enhancements to existing ones (UART0/1, Timers, ADC, and SPI) have been added. ...
Page 43
... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
Page 44
... NXP Semiconductors 15. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 Key features brought by LPC2109/2119/2129/01 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 Key features common for all devices . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 Functional description . . . . . . . . . . . . . . . . . . 10 6.1 Architectural overview ...