P89LPC915HDH NXP Semiconductors, P89LPC915HDH Datasheet
P89LPC915HDH
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P89LPC915/916/917 8-bit microcontrollers with accelerated two-clock 80C51 core flash with 8-bit A/D converter Rev. 05 — 15 December 2009 1. General description The P89LPC915/916/917 are single-chip microcontrollers, available in low-cost packages, based on a high performance ...
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... NXP Semiconductors I Serial Flash In-Circuit Programming (ICP) allows simple production coding with commercial EPROM programmers. Flash security bits prevent reading of sensitive application programs. I Watchdog timer with separate on-chip oscillator, requiring no external components. The Watchdog prescaler is selectable from 8 values. I Low voltage brownout detect allows a graceful system shutdown when power fails. ...
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... Ordering options Table 3. Type number P89LPC915FDH P89LPC915FN P89LPC916FDH P89LPC917FDH P89LPC915HDH [1] Please contact your local NXP sales office for availability of extended temperature ( +125 C) versions of the P89LPC916 and P89LPC917 devices. P89LPC915_916_917_5 Product data sheet 8-bit microcontrollers with accelerated two-clock 80C51 core Ordering information ...
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... NXP Semiconductors 5. Block diagram P89LPC915 2 kB CODE FLASH 256 BYTE DATA RAM P1[5:0] CONFIGURABLE I/O P0[5:0] CONFIGURABLE I/O KEYPAD INTERRUPT WATCHDOG TIMER AND OSCILLATOR PROGRAMMABLE OSCILLATOR DIVIDER external clock input ON-CHIP RC OSCILLATOR Fig 1. P89LPC915 block diagram P89LPC915_916_917_5 Product data sheet 8-bit microcontrollers with accelerated two-clock 80C51 core ...
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... NXP Semiconductors P89LPC916 2 kB CODE FLASH 256 BYTE DATA RAM P2[5:2] CONFIGURABLE I/O P1.5, P1[3:0] CONFIGURABLE I/O P0[5:1] CONFIGURABLE I/O KEYPAD INTERRUPT WATCHDOG TIMER AND OSCILLATOR PROGRAMMABLE OSCILLATOR DIVIDER external clock input ON-CHIP RC OSCILLATOR Fig 2. P89LPC916 block diagram P89LPC915_916_917_5 Product data sheet ...
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... NXP Semiconductors P89LPC917 2 kB CODE FLASH 256 BYTE DATA RAM P2.2 CONFIGURABLE I/O P1[5:0] CONFIGURABLE I/O P0.7, P[5:0] CONFIGURABLE I/O KEYPAD INTERRUPT WATCHDOG TIMER AND OSCILLATOR PROGRAMMABLE OSCILLATOR DIVIDER external clock input ON-CHIP RC OSCILLATOR clkout Fig 3. P89LPC917 block diagram P89LPC915_916_917_5 Product data sheet ...
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... NXP Semiconductors 6. Functional diagram KBI0 AD10 KBI1 AD11 KBI2 AD12 KBI3 AD13 DAC1 KBI4 CLKIN KBI5 Fig 4. P89LPC915 functional diagram AD10 KBI1 AD11 KBI2 AD12 KBI3 AD13 DAC1 KBI4 CLKIN KBI5 Fig 5. P89LPC916 functional diagram P89LPC915_916_917_5 Product data sheet 8-bit microcontrollers with accelerated two-clock 80C51 core ...
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... NXP Semiconductors KBI0 AD10 KBI1 AD11 KBI2 AD12 KBI3 AD13 DAC1 KBI4 CLKIN KBI5 CLKOUT KBI7 Fig 6. P89LPC917 functional diagram P89LPC915_916_917_5 Product data sheet 8-bit microcontrollers with accelerated two-clock 80C51 core V DD CMP2 CIN2B CIN2A CIN1B PORT 0 P89LPC917 CIN1A CMPREF T1 Rev. 05 — 15 December 2009 ...
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... NXP Semiconductors 7. Pinning information 7.1 Pinning Fig 7. Fig 8. Fig 9. P89LPC915_916_917_5 Product data sheet 8-bit microcontrollers with accelerated two-clock 80C51 core P0.1/CIN2B/KBI1/AD10 1 2 P0.0/CMP2/KBI0 P1.5/RST 3 P89LPC915 P1.4/INT1 P1.3/INT0/SDA 6 P1.2/T0/SCL 7 P89LPC915 TSSOP14 pin configuration 1 P0.1/CIN2B/KBI1/AD10 P0.0/CMP2/KBI0 2 P1.5/RST 3 P89LPC915 P1.4/INT1 5 6 P1.3/INT0/SDA P1.2/T0/SCL 7 P89LPC915 DIP14 pin confi ...
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... NXP Semiconductors Fig 10. P89LPC917 TSSOP16 pin configuration P89LPC915_916_917_5 Product data sheet 8-bit microcontrollers with accelerated two-clock 80C51 core 1 P0.1/CIN2B/KBI1/AD10 P0.0/CMP2/KBI0 2 P1.5/RST P89LPC917 5 P2.2 P1.4/INT1 6 P1.3/INT0/SDA 7 8 P1.2/T0/SCL Rev. 05 — 15 December 2009 P89LPC915/916/917 16 P0.2/CIN2A/KBI2/AD11 15 P0.3/CIN1B/KBI3/AD12 14 P0.4/CIN1A/KBI4/AD13/DAC1 13 P0.5/CMPREF/KBI5/CLKIN P0.7/T1/KBI7/CLKOUT 10 P1.0/TXD 9 P1.1/RXD 002aaa827 © ...
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... NXP Semiconductors 7.2 Pin description Table 4. P89LPC915 pin description Symbol Pin P0.0 to P0.5 P0.0/CMP2/KBI0 2 P0.1/CIN2B/KBI1/AD10 1 P0.2/CIN2A/KBI2/AD11 14 P0.3/CIN1B/KBI3/AD12 13 P0.4/CIN1A/KBI4/AD13/ 12 DAC1 P0.5/CMPREF/KBI5/CLKIN 11 P1.0 to P1.5 P89LPC915_916_917_5 Product data sheet 8-bit microcontrollers with accelerated two-clock 80C51 core Type Description I/O Port 0: Port 6-bit I/O port with a user-configurable output type. ...
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... NXP Semiconductors Table 4. P89LPC915 pin description Symbol Pin P1.0/TXD 9 P1.1/RXD 8 P1.2/T0/SCL 7 P1.3/INT0/SDA 6 P1.4/INT1 5 P1.5/RST [1] Input/output for P1.0 to P1.4. Input for P1.5. Table 5. P89LPC916 pin description Symbol Pin P0.0 to P0.5 P89LPC915_916_917_5 Product data sheet 8-bit microcontrollers with accelerated two-clock 80C51 core …continued ...
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... NXP Semiconductors Table 5. P89LPC916 pin description Symbol Pin P0.1/CIN2B/KBI1/AD10 1 P0.2/CIN2A/KBI2/AD11 16 P0.3/CIN1B/KBI3/AD12 15 P0.4/CIN1A/KBI4/AD13/DAC1 14 P0.5/CMPREF/KBI5/CLKIN 13 P1.0 to P1.5 P1.0/TXD 10 P1.1/RXD 9 P1.2/T0/SCL 8 P1.3/INT0/SDA 7 P1.5/RST 3 P89LPC915_916_917_5 Product data sheet 8-bit microcontrollers with accelerated two-clock 80C51 core …continued Type Description I/O P0.1 — Port 0 bit 1. I CIN2B — Comparator 2 positive input B. ...
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... NXP Semiconductors Table 5. P89LPC916 pin description Symbol Pin P2.2 to P2.5 P2.2/MOSI 6 P2.3/MISO 5 P2.4/SS 2 P2.5/SPICLK [1] Input/output for P1.0 to P1.3. Input for P1.5. P89LPC915_916_917_5 Product data sheet 8-bit microcontrollers with accelerated two-clock 80C51 core …continued Type Description I RST — External Reset input during power- selected via UCFG1. ...
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... NXP Semiconductors Table 6. P89LPC917 pin description Symbol Pin P0.0 to P0.5, P0.7 P0.0/CMP2/KBI0 2 P0.1/CIN2B/KBI1/AD10 1 P0.2/CIN2A/KBI2/AD11 16 P0.3/CIN1B/KBI3/AD12 15 P0.4/CIN1A/KBI4/AD13/ 14 DAC1 P0.5/CMPREF/KBI5 13 P89LPC915_916_917_5 Product data sheet 8-bit microcontrollers with accelerated two-clock 80C51 core Type Description I/O Port 0: Port 7-bit I/O port with a user-configurable output type. ...
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... NXP Semiconductors Table 6. P89LPC917 pin description Symbol Pin P0.7/T1/KBI7/CLKOUT 11 P1.0 to P1.5 P1.0/TXD 10 P1.1/RXD 9 P1.2/T0/SCL 8 P1.3/INT0/SDA 7 P1.4/INT1 6 P1.5/RST 3 P89LPC915_916_917_5 Product data sheet 8-bit microcontrollers with accelerated two-clock 80C51 core …continued Type Description I/O P0.7 — Port 0 bit 7. I/O T1 — Timer/counter 1 external count input or overflow output. ...
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... NXP Semiconductors Table 6. P89LPC917 pin description Symbol Pin P2 [1] Input/output for P1.0 to P1.4. Input for P1.5. P89LPC915_916_917_5 Product data sheet 8-bit microcontrollers with accelerated two-clock 80C51 core …continued Type Description Port 2: Port single bit I/O port with a user-configurable output type. ...
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... NXP Semiconductors 8. Functional description 8.1 Special function registers Remark: SFR accesses are restricted in the following ways: • User must not attempt to access any SFR locations not defined. • Accesses to any defined SFR locations must be strictly for the functions for the SFRs. ...
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Table 7. P89LPC915 special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. Bit address ACC* Accumulator E0H ADCON1 ADC control register 1 97H ADINS ADC input select A3H ADMODA ADC mode register A C0H ADMODB ...
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Table 7. P89LPC915 special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. FMCON Program flash control (Read) E4H Program flash control (Write) E4H FMDATA Program flash data E5H 2 I2ADR I C slave address register ...
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Table 7. P89LPC915 special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. Bit address P0* Port 0 80H Bit address P1* Port 1 90H Bit address P0M1 Port 0 output mode 1 84H P0M2 Port ...
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Table 7. P89LPC915 special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. Bit address TCON* Timer 0 and 1 control 88H TH0 Timer 0 high 8CH TH1 Timer 1 high 8DH TL0 Timer 0 low ...
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Table 8. P89LPC916 special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. Bit address ACC* Accumulator E0H ADCON1 ADC control register 1 97H ADINS ADC input select A3H ADMODA ADC mode register A C0H ADMODB ...
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Table 8. P89LPC916 special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. FMCON Program flash control (Read) E4H Program flash control (Write) E4H FMDATA Program flash data E5H 2 I2ADR I C slave address register ...
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Table 8. P89LPC916 special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. Bit address P0* Port 0 80H Bit address P1* Port 1 90H Bit address P2* Port 2 A0H P0M1 Port 0 output mode ...
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Table 8. P89LPC916 special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. SSTAT Serial port extended status BAH register SP Stack pointer 81H SPCTL SPI control register E2H SPSTAT SPI status register E1H SPDAT SPI ...
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Table 9. P89LPC917 special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. Bit address ACC* Accumulator E0H ADCON1 ADC control register 1 97H ADINS ADC input select A3H ADMODA ADC mode register A C0H ADMODB ...
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Table 9. P89LPC917 special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. FMCON Program flash control (Read) E4H Program flash control (Write) E4H FMDATA Program flash data E5H 2 I2ADR I C slave address register ...
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Table 9. P89LPC917 special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. Bit address P0* Port 0 80H Bit address P1* Port 1 90H Bit address P0M1 Port 0 output mode 1 84H (P0M1.7) P0M2 ...
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Table 9. P89LPC917 special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. Bit address TCON* Timer 0 and 1 control 88H TH0 Timer 0 high 8CH TH1 Timer 1 high 8DH TL0 Timer 0 low ...
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... NXP Semiconductors 8.2 Enhanced CPU The P89LPC915/916/917 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles. 8.3 Clocks 8.3.1 Clock definitions The P89LPC915/916/917 device has several internal clocks as defined below: OSCCLK — ...
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... NXP Semiconductors 8.6 External clock input option In this configuration, the processor clock is derived from an external source driving the CLKIN pin. The rate may be from MHz. When using an external clock input frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device ...
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... NXP Semiconductors 8.9 Low power select The P89LPC915/916/917 is designed to run at 18 MHz (CCLK) maximum. However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to ‘1’ to lower the power consumption further. On any reset, CLKLP is ‘0’ allowing highest performance access ...
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... NXP Semiconductors Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global disable bit, EA, which disables all interrupts. Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority ...
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... NXP Semiconductors RTCF ERTC (RTCCON.1) WDOVF TI_0 and RI_0/RI_0 TI_1 and RI_1/RI_1 ENADCI0 Fig 12. Interrupt sources, interrupt enables, and power-down wake-up sources P89LPC915_916_917_5 Product data sheet 8-bit microcontrollers with accelerated two-clock 80C51 core IE0 EX0 IE1 EX1 BOF EBO KBIF EKBI ...
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... NXP Semiconductors 8.13 I/O ports The P89LPC916 and P89LPC917 devices have three I/O ports: Port 0, Port 1, and Port 2. The exact number of I/O pins available depends upon the clock and reset options chosen, as shown in Table 11. Clock source RC oscillator or watchdog oscillator External clock input [1] Required for operation above 12 MHz ...
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... NXP Semiconductors The P89LPC915/916/917 device, but the pins are 5 V tolerant. In quasi-bidirectional mode user applies the pin, there will be a current flowing from the pin to V quasi-bidirectional mode is discouraged. A quasi-bidirectional port pin has a Schmitt triggered input that also has a glitch suppression circuit. ...
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... NXP Semiconductors All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals. The slew rate is factory-set to approximately 10 ns rise and fall times. 8.14 Power monitoring functions The P89LPC915/916/917 incorporates power monitoring functions designed to prevent incorrect operation during initial power-up and power loss or reduction during operation ...
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... NXP Semiconductors Some chip functions continue to operate and draw power during Power-down mode, increasing the total power used during power-down. These include: Brownout detect, watchdog timer, comparators (note that comparators can be powered down separately), and RTC/system timer. The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock and the RTC is enabled ...
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... NXP Semiconductors In the ‘Timer’ function, the register is incremented every machine cycle. In the ‘Counter’ function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin T1. In this function, the external input is sampled once during every machine cycle. Timer 0 has five operating modes (Modes and 6). ...
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... NXP Semiconductors The clock source for this counter can be either the CPU clock (CCLK) or the external clock input, provided that the external clock input is not being used as the CPU clock. If the external clock input is used as the CPU clock, then the RTC will use CCLK as its clock source ...
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... NXP Semiconductors 8.19.5 Baud rate generator and selection Each enhanced UART has an independent Baud Rate Generator. The baud rate is determined by a baud-rate preprogrammed into the BRGR1 and BRGR0 SFRs which together form a 16-bit baud rate divisor value that works in a similar manner as Timer 1 but is much more accurate ...
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... NXP Semiconductors th 8.19.10 The 9 If double buffering is disabled TB8 can be written before or after SBUF is written, as long as TB8 is updated some time before that bit is shifted out. TB8 must not be changed until the bit is shifted out, as indicated by the TI interrupt. If double buffering is enabled, TB must be updated before SBUF is written, as TB8 will be double-buffered together with SBUF data ...
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... NXP Semiconductors P1.3/SDA P1.2/SCL Fig 15. I P89LPC915_916_917_5 Product data sheet 8-bit microcontrollers with accelerated two-clock 80C51 core P1.3 INPUT FILTER OUTPUT STAGE INPUT FILTER OUTPUT STAGE timer 1 overflow P1.2 I2CON I2SCLH I2SCLL status bus I2STAT 2 C-bus serial interface block diagram Rev. 05 — 15 December 2009 ...
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... NXP Semiconductors 8.21 SPI The P89LPC916 provides another high-speed serial communication interface—the SPI interface. SPI is a full-duplex, high-speed, synchronous communication bus with two operation modes: Master mode and Slave mode 4.5 Mbit/s can be supported in Master mode Mbit/s in Slave mode. It has a Transfer Completion Flag and Write Collision Flag Protection ...
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... NXP Semiconductors 8.21.1 Typical SPI configurations Fig 17. SPI single master single slave configuration Fig 18. SPI dual device configuration, where either can be a master or a slave P89LPC915_916_917_5 Product data sheet 8-bit microcontrollers with accelerated two-clock 80C51 core master MISO ...
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... NXP Semiconductors Fig 19. SPI single master multiple slaves configuration P89LPC915_916_917_5 Product data sheet 8-bit microcontrollers with accelerated two-clock 80C51 core master MISO 8-BIT SHIFT MOSI REGISTER SPICLK SPI CLOCK port GENERATOR port Rev. 05 — 15 December 2009 P89LPC915/916/917 slave MISO 8-BIT SHIFT ...
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... NXP Semiconductors 8.22 Analog comparators Two analog comparators are provided on the P89LPC915/916/917. Input and output options allow use of the comparators in a number of different configurations. Comparator operation is such that the output is a logical one when the positive input is greater than the negative input (selectable from a pin or an internal reference voltage). Otherwise the output is a zero. Each comparator may be confi ...
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... NXP Semiconductors If a comparator interrupt is enabled (except in Total Power-down mode), a change of the comparator output state will generate an interrupt and wake-up the processor. If the comparator output to a pin is enabled, the pin should be configured in the push-pull mode in order to obtain fast switching times while in Power-down mode. The reason is that with the oscillator stopped, the temporary strong pull-up that normally occurs during switching on a quasi-bidirectional port pin does not take place ...
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... NXP Semiconductors 8.24 Watchdog timer The watchdog timer causes a system reset when it underflows as a result of a failure to feed the timer prior to the timer reaching its terminal count. It consists of a programmable 12-bit prescaler, and an 8-bit down-counter. The down-counter is decremented by a tap taken from the prescaler ...
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... NXP Semiconductors 8.26 Flash program memory 8.26.1 General description The P89LPC915/916/917 flash memory provides in-circuit electrical erasure and programming. The flash can be erased, read, and written as bytes. The Sector and Page Erase functions can erase any flash sector (256 bytes) or page (16 bytes). The Chip Erase operation will erase the entire program memory ...
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... NXP Semiconductors 8.26.6 ICP ICP is performed without removing the microcontroller from the system. The ICP facility consists of internal hardware resources to facilitate remote programming of the P89LPC915/916/917 through a two-wire serial interface. The NXP ICP facility has made in-circuit programming in an embedded application—using commercially available programmers— ...
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... NXP Semiconductors 8.28 User sector security bytes There are eight User Sector Security Bytes on the P89LPC915/916/917. Each byte corresponds to one sector. Please see the P89LPC915/916/917 User’s Manual for additional details. 9. A/D converter 9.1 General description The P89LPC915/916/917 devices have a single 8-bit, 4-channel multiplexed analog-to-digital converter with a DAC module ...
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... NXP Semiconductors 9.3 Block diagram Fig 22. ADC block diagram 9.4 A/D operating modes 9.4.1 Fixed channel, single conversion mode A single input channel can be selected for conversion. A single conversion will be performed and the result placed in the result register which corresponds to the selected input channel ...
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... NXP Semiconductors 9.4.4 Auto scan, continuous conversion mode Any combination of the four input channels can be selected for conversion. A conversion of each selected input will be performed and the result placed in the result register which corresponds to the selected input channel. An interrupt, if enabled, will be generated after all selected channels have been converted. The process will repeat starting with the fi ...
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... NXP Semiconductors 9.7 DAC output to a port pin with high output impedance The A/D converter’s DAC block can be output to a port pin. In this mode, the AD1DAT3 register is used to hold the value fed to the DAC. After a value has been written to the DAC (written to AD1DAT3), the DAC output will appear on the channel 3 pin ...
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... NXP Semiconductors 10. Limiting values Table 14. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter T operating bias ambient temperature amb(bias) T storage temperature range stg I HIGH-level output current per I/O pin OH(I/O) I LOW-level output current per I/O pin OL(I/O) ...
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... NXP Semiconductors 11. Static characteristics Table 15. Static characteristics 3.6 V unless otherwise specified + +125 C (see amb Symbol Parameter I operating supply current DD(oper) I Idle mode supply current DD(idle) I power supply current, DD(pd) power-down mode, voltage comparators powered-down I total Power-down mode DD(tpd) supply current ...
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... NXP Semiconductors Table 15. Static characteristics 3.6 V unless otherwise specified + +125 C (see amb Symbol Parameter I input leakage current LI I logical 1-to-0 transition TL current, all ports R internal pull-up resistance RST(int) on pin RST V brownout trip voltage bo V band gap reference voltage ref(bg) ...
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... NXP Semiconductors 12. Dynamic characteristics Table 16. Dynamic characteristics (12 MHz 2 3.6 V unless otherwise specified + +125 C (see amb Symbol Parameter f internal RC oscillator frequency osc(RC) f internal watchdog oscillator osc(WD) frequency f low power select clock CLKLP frequency Glitch filter t glitch rejection time gr t signal acceptance time ...
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... NXP Semiconductors Table 16. Dynamic characteristics (12 MHz 2 3.6 V unless otherwise specified + +125 C (see amb Symbol Parameter t SPI enable lead time SPILEAD slave t SPI enable lag time SPILAG slave t SPICLK HIGH time SPICLKH master slave t SPICLK LOW time SPICLKL master slave t SPI data set-up time ...
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... NXP Semiconductors Table 17. Dynamic characteristics (18 MHz 3 3.6 V unless otherwise specified + +125 C (see amb Symbol Parameter f internal RC oscillator frequency industrial osc(RC) f internal watchdog oscillator osc(WD) frequency f low power select clock CLKLP frequency Glitch filter t glitch rejection time gr t signal acceptance time ...
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... NXP Semiconductors Table 17. Dynamic characteristics (18 MHz 3 3.6 V unless otherwise specified + +125 C (see amb Symbol Parameter t SPICLK HIGH time SPICLKH master slave t SPICLK LOW time SPICLKL master slave t SPI data set-up time SPIDSU master or slave t SPI data hold time SPIDH master or slave ...
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... NXP Semiconductors 12.1 Waveforms SS SPICLK (CPOL = 0) (output) SPICLK (CPOL = 1) (output) MISO (input) t MOSI SPIF (output) Fig 23. SPI master timing (CPHA = 0) SS SPICLK (CPOL = 0) (output) SPICLK (CPOL = 1) (output) MISO (input) t SPIF MOSI (output) Fig 24. SPI master timing (CPHA = 1) P89LPC915_916_917_5 Product data sheet ...
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... NXP Semiconductors SS t SPIF t SPILEAD SPICLK (CPOL = 0) (input) t SPIF SPICLK (CPOL = 1) (input) t SPIA MISO (output) t SPIDSU MOSI (input) Fig 25. SPI slave timing (CPHA = SPIF t SPILEAD SPICLK (CPOL = 0) (input) t SPIF SPICLK (CPOL = 1) (input) t SPIOH t SPIDV t SPIA MISO not defined (output) MOSI (input) Fig 26 ...
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... NXP Semiconductors clock t QVXH output data write to SBUF t XHDV input data clear RI Fig 27. Shift register mode timing Fig 28. External clock timing 12.2 ISP entry mode Table 18. Dynamic characteristics, ISP entry mode 3.6 V, unless otherwise specified + +125 C (see amb Symbol ...
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... NXP Semiconductors 13. Other characteristics 13.1 Comparator electrical characteristics Table 19. Comparator electrical characteristics 3.6 V, unless otherwise specified + +125 C (see amb Symbol Parameter V input offset voltage IO V common mode input voltage IC CMRR common mode rejection ratio t total response time res(tot) t chip enable to output valid time ...
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... NXP Semiconductors 14. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...
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... NXP Semiconductors TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 15. Abbreviations Table 21. Acronym ADC CPU CCU DAC EPROM EEPROM EMI PLL PWM RAM RC RTC SAR SFR SPI UART P89LPC915_916_917_5 Product data sheet 8-bit microcontrollers with accelerated two-clock 80C51 core Acronym list Description Analog to Digital Converter Central Processing Unit Capture/Compare Unit ...
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... Release date P89LPC915_916_917_5 20091215 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Added ADC electrical characteristics, • ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 Principal features . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 Additional features . . . . . . . . . . . . . . . . . . . . . . 1 3 Product comparison overview . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 7 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 9 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 11 8 Functional description . . . . . . . . . . . . . . . . . . 18 8.1 Special function registers ...
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... NXP Semiconductors 9.4 A/D operating modes . . . . . . . . . . . . . . . . . . . 54 9.4.1 Fixed channel, single conversion mode . . . . . 54 9.4.2 Fixed channel, continuous conversion mode . 54 9.4.3 Auto scan, single conversion mode . . . . . . . . 54 9.4.4 Auto scan, continuous conversion mode . . . . 55 9.4.5 Dual channel, continuous conversion mode . . 55 9.4.6 Single step mode . . . . . . . . . . . . . . . . . . . . . . 55 9.5 Conversion start modes ...