ST62T15CM6 STMicroelectronics, ST62T15CM6 Datasheet - Page 29

• Manufacturer Part Number: ST62T15CM6
• Description: 8BIT MCU OTP 2K, SMD, 62T15, SOIC20
• Manufacturer: STMicroelectronics

Specifications of ST62T15CM6

• Controller Family/series: ST6
• Core Size: 8bit
• No. Of I/o's: 20
• Program Memory Size: 2KB
• Ram Memory Size: 64Byte
• Cpu Speed: 8MHz
• Oscillator Type: External Only
• No. Of Timers: 1
• Digital Ic Case: RoHS Compliant
• Peripherals: ADC,
• Rohs Compliant: No
• Processor Series: ST62T1x
• Core: ST6
• Data Bus Width: 8 bit
• Program Memory Type: EPROM
• Data Ram Size: 64 B
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 20
• Number Of Timers: 2
• Operating Supply Voltage: 3 V to 6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOP-28
• Development Tools By Supplier: ST62GP-EMU2, ST62E2XC-EPB/110, ST62E6XC-EPB/US, STREALIZER-II
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / Rohs Status: In Transition

6.1
MANAGEMENT
6.2 INTERRUPTS AND LOW POWER MODES
All interrupts cause the processor to exit from
WAIT mode. Only the external and some specific
interrupts from the on-chip peripherals cause the
processor to exit from STOP mode (refer to the
“Exit from STOP“ column in the Interrupt Mapping
Table).
A Reset can interrupt the NMI and peripheral
interrupt routines
The Non Maskable Interrupt request has the
highest priority and can interrupt any peripheral
interrupt routine at any time but cannot interrupt
another NMI interrupt.
No peripheral interrupt can interrupt another. If
more than one interrupt request is pending,
these are processed by the processor core
according to their priority level: vector #1 has the
highest priority while vector #4 the lowest. The
priority of each interrupt source is fixed by
hardware (see
INTERRUPT
Interrupt Mapping
RULES
AND
table).
PRIORITY
6.3 NON MASKABLE INTERRUPT
This interrupt is triggered when a falling edge oc-
curs on the NMI pin regardless of the state of the
GEN bit in the IOR register. An interrupt request
on NMI vector #0 is latched by a flip flop which is
automatically reset by the core at the beginning of
the NMI service routine.
6.4 PERIPHERAL INTERRUPTS
Different peripheral interrupt flags in the peripheral
control registers are able to cause an interrupt
when they are active if both:
– The GEN bit of the IOR register is set
– The corresponding enable bit is set in the periph-
Peripheral interrupts are linked to vectors #3 and
#4. Interrupt requests are flagged by a bit in their
corresponding control register. This means that a
request cannot be lost, because the flag bit must
be cleared by user software.
eral control register.
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