CS5524-AS Cirrus Logic Inc, CS5524-AS Datasheet - Page 13
![A/D Converter (A-D) IC](/photos/19/0/190076/3833506_sml.gif)
CS5524-AS
Manufacturer Part Number
CS5524-AS
Description
A/D Converter (A-D) IC
Manufacturer
Cirrus Logic Inc
Datasheet
1.CS5524-AS.pdf
(56 pages)
Specifications of CS5524-AS
Sample Rate
606SPS
Input Channels Per Adc
4
Mounting Type
Surface Mount
No. Of Channels
4
Power Rating
9mW
Peak Reflow Compatible (260 C)
No
Supply Voltage Max
5.25V
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS5524-ASZ
Manufacturer:
CIRRUS
Quantity:
20 000
2. GENERAL DESCRIPTION
The CS5521/22/23/24/28 are highly integrated
Analog-to-Digital Converters (ADCs) which use
charge-balance techniques to achieve 16-bit
(CS5521/23) and 24-bit (CS5522/24/28) perfor-
mance. The ADCs come as either two-channel
(CS5521/22), four-channel (CS5523/24), or eight-
channel (CS5528) devices, and include a low input
current, chopper-stabilized instrumentation ampli-
fier. To permit selectable input spans of 25 mV,
55 mV, 100 mV, 1 V, 2.5 V, and 5 V, the ADCs in-
clude a PGA (programmable gain amplifier). To
accommodate ground-based thermocouple applica-
tions, the devices include a CPD (Charge Pump
Drive) which provides a negative bias voltage to
the on-chip amplifiers.
These devices also include a fourth order DS mod-
ulator followed by a digital filter which provides
eight selectable output word rates of 1.88 Hz,
3.76 Hz, 7.51 Hz, 15 Hz, 30 Hz, 61.6 Hz, 84.5 Hz,
and 101.1 Hz (XIN = 32.768 kHz). The devices are
capable of producing output update rates up to
617 Hz
(CS5522/24/28) or up to 401 Hz using a 130 kHz
DS317F2
when
a
AIN2+
AIN1+
AIN4+
AIN1+
AIN8+
AIN7+
AIN1+
AIN2-
AIN1-
AIN4-
AIN1-
200 kHz
NBV
*
*
*
*
*
*
CS5522
CS5524
CS5528
M
U
M
U
M
U
X
X
X
clock
IN+
IN-
IN+
IN-
IN+
IN-
Figure 4. Multiplexer Configurations
IN+
IN-
is
used
X20
clock (CS5521/23). Further note that the digital fil-
ters are designed to settle to full accuracy within
one conversion cycle and simultaneously reject
both 50 Hz and 60 Hz interference when operated
at word rates below 30 Hz (assuming a XIN clock
frequency of 32.768 kHz).
To ease communication between the ADCs and a
micro-controller, the converters include an easy to
use three-wire serial interface which is SPI™ and
Microwire™ compatible.
2.1 Analog Input
Figure 4 illustrates a block diagram of the analog in-
put signal path inside the CS5521/22/23/24/28. The
front end consists of a multiplexer (break before
make configuration), a chopper-stabilized instru-
mentation amplifier with fixed gain of 20X,
coarse/fine charge buffers, and a programmable gain
section. For the 25 mV, 55 mV, and 100 mV input
ranges, the input signals are amplified by the 20X in-
strumentation amplifier. For the 1 V, 2.5 V, and 5 V
input ranges, the instrumentation amplifier is by-
passed and the input signals are connected to the
Programmable Gain block via coarse/fine charge
buffers.
NBV also supplies the negative
supply voltage for the coarse/fine
change buffers
Programmable
Gain
VREF+
delta-sigma
Differential
modulator
4th order
VREF-
CS5521/22/23/24/28
Digital
Filter
13