CS5524-AS Cirrus Logic Inc, CS5524-AS Datasheet - Page 30

• Manufacturer Part Number: CS5524-AS
• Description: A/D Converter (A-D) IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5524-AS

• Sample Rate: 606SPS
• Input Channels Per Adc: 4
• Mounting Type: Surface Mount
• No. Of Channels: 4
• Power Rating: 9mW
• Peak Reflow Compatible (260 C): No
• Supply Voltage Max: 5.25V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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* R indicates the bit value after the part is reset
D23-D22
D21-D20
D19
D18
D17
D16
D15-D12
D11
D10
D9
D8
D7
D6
D5
D4
D3-D0
D23(MSB)
BIT
PSS
D11
NU
Not Used, NU
Chop Frequency Select,
CFS1-CFS0
Not Used, NU
Multiple Conversion, MC
Loop, LP
Read Convert, RC
Depth Pointer, DP3-DP0
Power Save Select, PSS
Pump Disable, PD
Power Save/Run, PS/R
Low Power Mode, LPM
Reset System, RS
Reset Valid, RV
Oscillation Detect, OD
Overrange Flag, OF
Not Used, NU
D22
D10
NU
PD
NAME
CFS1
PS/R
D21
D9
CFS0
LPM
D20
D8
VALUE
0000
0000
1111
00
00
01
10
11
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
.
.
Table 4. Configuration Register
D19
NU
RS
D7
R* Must always be logic 0.
R 256 Hz Amplifier chop frequency.
R Must always be logic 0.
R Perform single-Setup conversions. MC bit is ignored during calibrations.
R The conversions on the single Setup (MC = 0) or multiple Setups (MC =
R Don’t wait for user to finish reading data before starting new conversions.
R When writing or reading the CSRs, these bits (DP3-DP0) determine the
R Standby Mode (Oscillator active, allows quick power-up).
R Charge Pump Enabled.
R Run.
R Normal Mode (LPM bit is only for the CS5522/24/28)
R Normal Operation.
R
R Bit is clear when an oscillation condition has not occurred (read only).
R Bit is clear when an overrange condition has not occurred (read only).
R Must always be logic 0.
4,096 Hz Amplifier chop frequency.
16,384 Hz Amplifier chop frequency.
1,024 Hz Amplifier chop frequency.
Perform multiple-Setup conversions on Setups in the channel-setup reg-
ister by issuing only one command with MSB = 1.
1) are performed only once.
The conversions on the single Setup (MC = 0) or multiple Setups (MC =
1) are continuously performed.
The RC bit is used in conjunction with the LP bit when the LP bit is set to
logic 1. If LP = 0, the RC bit is ignored. If LP = 1, the ADC waits for user to
read data conversion(s) before converting again. The RC bit is ignored
during calibrations. Refer to Calibration Protocol for details.
number of CSR’s to be accessed. They are also used to determine how
many Setups are converted when MC=1 and a command byte with its
MSB = 1 is issued. Note that the CS5522 has two CSRS, the CS5524 has
four CSRs, and the CS5528 has 8 CSRs.
Sleep Mode (Oscillator inactive).
For PD = 1, the CPD pin goes to a Hi-Z output state.
Power Save.
Reduced Power Mode
Activate a Reset cycle. To return to Normal Operation write bit to zero.
No reset has occurred or bit has been cleared (read only).
Bit is set after a Valid Reset has occurred. (Cleared when read.)
Bit is set when an oscillatory condition is detected in the modulator.
Bit is set when input signal is more positive than the positive full scale,
more negative than zero (unipolar mode), or when the input is more neg-
ative than the negative full scale (bipolar mode).
D18
MC
D6
RV
D17
OD
LP
D5
D16
RC
OF
D4
FUNCTION
DP3
D15
NU
D3
CS5521/22/23/24/28
DP2
D14
NU
D2
(XIN = 32.768 kHz)
DP1
D13
NU
D1
DS317F2
DP0
D12
NU
D0