CS5524-AS Cirrus Logic Inc, CS5524-AS Datasheet - Page 16

• Manufacturer Part Number: CS5524-AS
• Description: A/D Converter (A-D) IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5524-AS

• Sample Rate: 606SPS
• Input Channels Per Adc: 4
• Mounting Type: Surface Mount
• No. Of Channels: 4
• Power Rating: 9mW
• Peak Reflow Compatible (260 C): No
• Supply Voltage Max: 5.25V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

mentation amplifier, typically 100 pA, is low
enough to permit large external resistors to divide
down a large external signal without significant
loading. Figure 7 illustrates an example circuit. Re-
fer to Applications Note 158 for more details on
high voltage (>5 V) measurement.
2.1.5 Voltage Reference
The CS5521/22/23/24/28 are specified for opera-
tion with a 2.5 V reference voltage between the
VREF+ and VREF- pins of the device. For a single-
ended reference voltage, such as the LT1019-2.5,
the reference voltage is input into the VREF+ pin
of the converter and the VREF- pin is grounded.
The differential voltage between the VREF+ and
VREF- can be any voltage from 1.0 V up to VA+,
however, the VREF+ cannot go above VA+ and the
VREF- pin can not go below NBV.
Figure 8 illustrates the input models for the VREF
pins. The dynamic input current for each of the pins
can be determined from the models shown.
16
±10V
chop clock = 256 Hz
1 M
Voltage
+5 V
Divider
PGIA set for
+ 100 mV
Figure 7. Input Ranges Greater than 5 V
2.5 V
10 K
BAT85
V
0.1 F
-2.1 V
NBV
VREF+
VREF-
+
-
PGIA
VA+
+
1N4148
10 F
10
Charge Pump
Regulator
CPD
ADC
1N4148
0.033 F
VD+
DGND
Charge Pump
Circuitry
0.1 F
2.2 Overview of ADC Register Structure
and Operating Modes
The CS5521/22/23/24/28 ADCs have an on-chip
controller, which includes a number of user-acces-
sible registers. The registers are used to hold offset
and gain calibration results, configure the chip’s
operating modes, hold conversion instructions, and
to store conversion data words. Figure 9 depicts a
block diagram of the on-chip controller’s internal
registers for the CS5523/24.
Each of the converters has 24-bit registers to func-
tion as offset and gain calibration registers for each
channel. The converters with two channels have
two offset and two gain calibration registers, the
converters with four channels have four offset and
four gain calibration registers, and the eight chan-
nel converter has eight offset and eight gain cali-
bration registers. These registers hold calibration
results. The contents of these registers can be read
or written by the user. This allows calibration data
to be off-loaded into an external EEPROM. The
user can also manipulate the contents of these reg-
isters to modify the offset or the gain slope of the
converter.
The converters include a 24-bit configuration reg-
ister of which 17 of the bits are used for setting op-
tions such as the conversion mode, operating power
options, setting the chop clock rate of the instru-
mentation amplifier, and providing a number of
flags which indicate converter operation.
Figure 8. Input Model for VREF+ and VREF- Pins
V
i = fV
n
os
VREF
25mV
os
C
f = 32.768 kHz
CS5521/22/23/24/28
2
C = 10pF
Coarse
1
Fine
DS317F2