CS5524-AS Cirrus Logic Inc, CS5524-AS Datasheet - Page 31

• Manufacturer Part Number: CS5524-AS
• Description: A/D Converter (A-D) IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5524-AS

• Sample Rate: 606SPS
• Input Channels Per Adc: 4
• Mounting Type: Surface Mount
• No. Of Channels: 4
• Power Rating: 9mW
• Peak Reflow Compatible (260 C): No
• Supply Voltage Max: 5.25V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

2.3 Calibration
The CS5521/22/23/24/28 offer four different cali-
bration functions including self calibration and sys-
tem calibration. However, after the devices are
reset, the converter is functional and can perform
measurements without being calibrated. In this
case, the converter will utilize the initialized values
of the on-chip registers (Gain = 1.0, Offset = 0.0)
to calculate output words for the 100 mV range.
Any initial offset and gain errors in the internal cir-
cuitry of the chip will remain.
The gain and offset registers, which are used for
both self and system calibration, are used to set the
zero and full-scale points of the converter’s transfer
function. One LSB in the offset register is 2
portion of the input span when the gain register is
set to 1.0 decimal (bipolar span is 2 times the uni-
polar span). The MSB in the offset register deter-
mines if the offset to be trimmed is positive or
negative (0 positive, 1 negative). The converter can
typically trim ±50 percent of the input span. The
DS317F2
Offset Register
One LSB represents 2
Offset and data word bits align by MSB (bit MSB-4 of offset register changes bit MSB-4 of data)
Gain Register
The gain register span is from 0 to (4-2
Register
Reset (R)
Register
Reset (R)
2 times unipolar span)
MSB
MSB
Sign
2
0
0
1
-24
2
2
1
0
0
-2
proportion of the input span when gain register is set to 1.0 decimal (bipolar span is
2
2
0
-1
0
-3
2
2
0
0
-2
-4
Table 5. Offset and Gain Registers
-22
2
). After Reset the (MSB-1) bit is 1, all other bits are 0.
2
0
0
-3
-5
-24
pro-
2
2
0
-4
0
-6
gain register spans from 0 to (4 - 2
equivalent meaning of the gain register is:
where the binary numbers have a value of either
zero or one (b
Refer to Table 5 for details.
The offset and gain calibration steps each take one
conversion cycle to complete. At the end of the cal-
ibration step, SDO falls to indicate that the calibra-
tion has finished.
2.3.1 Self Calibration
The CS5521/22/23/24/28 offer both self offset and
self gain calibrations. For the self-calibration of
offset in the 25 mV, 55 mV, and 100 mv ranges,
the converters internally tie the inputs of the instru-
mentation amplifier together and route them to the
AIN- pin as shown in Figure 11 (in the CS5528
they are routed to AGND). For proper self-calibra-
2
2
-17
0
-19
0
D
=
b
MSB
2
2
-18
0
-20
0
2
1
+
b
0
2
0
2
-19
0
2
-21
0
corresponds to bit MSB-1, N=22).
0
+
b
1
CS5521/22/23/24/28
2
1 –
2
2
-20
0
-22
0
+
+
b
N
2
2
2
-21
0
-23
0
–
N
=
-22
b
LSB
2
LSB
MSB
2
-22
0
). The decimal
-24
0
2
1
+
i
=
N
0
b
i
2
i –
31