PIC16F946T-I/PT Microchip Technology, PIC16F946T-I/PT Datasheet
PIC16F946T-I/PT
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PIC16F946T-I/PT Summary of contents
Page 1
... LCD Driver and nanoWatt Technology © 2005 Microchip Technology Inc. PIC16F946 Data Sheet 64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with Preliminary DS41265A ...
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... PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance and WiperLock are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Multiplexed Master Clear with pull-up/input pin • Programmable code protection • High-Endurance Flash/EEPROM cell: - 100,000 write Flash endurance - 1,000,000 write EEPROM endurance - Flash/Data EEPROM retention: > 40 years © 2005 Microchip Technology Inc. PIC16F946 Low-Power Features: • Standby Current: - <100 nA @ 2.0V, typical • Operating Current ...
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... RF1/SEG33 12 RF2/SEG34 13 RF3/SEG35 14 RB0/INT/SEG0 15 RB1/SEG1 DS41265A-page 2 10-bit A/D I/O (segment (ch) EEPROM drivers) (bytes) 256 PIC16F946 Preliminary LCD Timers CCP 8/16-bit 42 2 2/1 48 RF7/SEG31 47 RF6/SEG30 46 RF5/SEG29 45 RF4/SEG28 44 RE7/SEG27 43 RE6/SEG26 RE5/SEG25 RA6/OSC2/CLKO/T1OSO 39 RA7/OSC1/CLKI/T1OSI RE4/SEG24 36 RE3/MCLR RE2/AN7/SEG23 34 RE1/AN6/SEG22 33 RE0/AN5/SEG21 © 2005 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2005 Microchip Technology Inc. Preliminary PIC16F946 DS41265A-page 3 ...
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... PIC16F946 NOTES: DS41265A-page 4 Preliminary © 2005 Microchip Technology Inc. ...
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... The PIC16F946 devices are covered by this data sheet available in a 64-pin package. Figure 1-1 shows a block diagram of the device and Table 1-1 shows the pinout description. © 2005 Microchip Technology Inc. for a better Preliminary PIC16F946 ...
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... RD4/SEG17 RD5/SEG18 RD6/SEG19 RD7/SEG20 PORTE RE0/AN5/SEG21 RE1/AN6/SEG22 RE2/AN7/SEG23 RE3/MCLR/V PP RE4/SEG24 RE5/SEG25 RE6/SEG26 RE7/SEG27 PORTF RF0/SEG32 RF1/SEG33 RF2/SEG34 RF3/SEG35 RF4/SEG28 RF5/SEG29 RF6/SEG30 RF7/SEG31 PORTG RG0/SEG36 RG1/SEG37 RG2/SEG38 RG3/SEG39 RG4/SEG40 RG5/SEG41 Data EEPROM 256 bytes BOR PLVD LCD © 2005 Microchip Technology Inc. ...
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... INT SEG0 RB1/SEG1 RB1 SEG1 RB2/SEG2 RB2 SEG2 Legend Analog input or output TTL = TTL compatible input HV = High Voltage © 2005 Microchip Technology Inc. Input Output Type Type TTL CMOS General purpose I/O. AN — Analog input Channel 0/Comparator 1 input – negative. — AN Comparator 1 negative input. — ...
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... CMOS USART asynchronous serial transmit. ST CMOS USART synchronous serial clock. ST CMOS SPI™ clock CMOS I C™ clock. — AN LCD analog output. CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels XTAL = Crystal Preliminary Description D = Direct © 2005 Microchip Technology Inc. ...
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... RE6 SEG26 RE7/SEG27 RE7 SEG27 RF0/SEG32 RF0 SEG32 Legend Analog input or output TTL = TTL compatible input HV = High Voltage © 2005 Microchip Technology Inc. Input Output Type Type ST CMOS General purpose I/O. ST — USART asynchronous serial receive. ST CMOS USART synchronous serial data. ...
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... LCD analog output. ST CMOS General purpose I/O. — AN LCD analog output. D — Power supply for microcontroller. D — Ground reference for microcontroller. CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels XTAL = Crystal Preliminary Description D = Direct © 2005 Microchip Technology Inc. ...
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... Page 1 On-chip Program Memory Page 2 Page 3 © 2005 Microchip Technology Inc. 2.2 Data Memory Organization The data memory is partitioned into multiple banks which contain the General Purpose Registers (GPRs) and the Special Function Registers (SFRs). Bits RP0 and RP1 are bank select bits. ...
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... LCDDATA15 193h LCDDATA16 194h LCDDATA17 195h LCDDATA18 196h LCDDATA19 197h LCDDATA20 198h LCDDATA21 199h LCDDATA22 19Ah LCDDATA23 19Bh LCDSE3 19Ch LCDSE4 19Dh LCDSE5 19Eh 19Fh General 1A0h Purpose Register 80 Bytes 1EFh accesses 1F0h 70h-7Fh 1FFh Bank 3 © 2005 Microchip Technology Inc. ...
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... VCFG1 VCFG0 Legend: – = Unimplemented locations read as ‘0’ unchanged unknown value depends on condition, shaded = unimplemented Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. © 2005 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 RP0 TO ...
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... TRMT TX9D 0000 -010 0000 -010 SPBRG0 0000 0000 0000 0000 — — — — CM1 CM0 0000 0000 0000 0000 VR1 VR0 0-0- 0000 0-0- 0000 xxxx xxxx uuuu uuuu — — -000 ---- -000 --- © 2005 Microchip Technology Inc. ...
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... Unimplemented locations read as ‘0’ unchanged unknown value depends on condition, shaded = unimplemented Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. 2: This register is only initialized by a POR or BOR reset and is unchanged by other Resets. © 2005 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 RP0 ...
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... COM2 SEG40 ---- --xx ---- --uu COM2 SEG24 xxxx xxxx uuuu uuuu COM3 SEG32 xxxx xxxx uuuu uuuu COM3 SEG40 ---- --xx ---- --uu COM3 SE24 0000 0000 uuuu uuuu SE32 0000 0000 uuuu uuuu SE40 ---- --00 ---- --uu — — © 2005 Microchip Technology Inc. ...
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... Legend Readable bit - n = Value at POR © 2005 Microchip Technology Inc. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the Status register as ‘000u u1uu’ (where u = unchanged). ...
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... R/W-1 T0CS T0SE PSA TMR0 Rate WDT Rate 128 256 1 : 128 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 R/W-1 PS2 PS1 PS0 bit Bit is unknown © 2005 Microchip Technology Inc. ...
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... T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before clearing T0IF bit. Legend Readable bit - n = Value at POR © 2005 Microchip Technology Inc. Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON< ...
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... Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. R/W-0 R/W-0 R/W-0 R/W-0 RCIE TXIE SSPIE CCP1IE W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 TMR2IE TMR1IE bit Bit is unknown © 2005 Microchip Technology Inc. ...
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... CCP2IE: CCP2 Interrupt Enable bit (only available in PIC16F914/917 Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt Legend Readable bit - n = Value at POR © 2005 Microchip Technology Inc. Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. R/W-0 R/W-0 U-0 C2IE ...
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... R-0 R-0 R/W-0 R/W-0 RCIF TXIF SSPIF CCP1IF W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary © 2005 Microchip Technology Inc. R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown ...
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... No TMR1 register compare match occurred PWM mode: Unused in this mode Legend Readable bit - n = Value at POR © 2005 Microchip Technology Inc. Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User ...
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... Value at POR DS41265A-page 24 U-0 U-0 R/W-1 U-0 — — SBOREN — ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary U-0 R/W-0 R/W-x — POR BOR bit Bit is unknown © 2005 Microchip Technology Inc. ...
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... PUSHed eight times, the ninth PUSH overwrites the value that was stored from the first PUSH. The tenth PUSH overwrites the second PUSH (and so on). © 2005 Microchip Technology Inc. Note 1: There are no Status bits to indicate stack overflow or stack underflow conditions. 2: There are no instructions/mnemonics called PUSH or POP ...
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... Bank 1 Bank 2 Bank 3 Preliminary INDIRECT ADDRESSING 0x20 ;initialize pointer FSR ;to RAM INDF ;clear INDF register FSR ;inc pointer FSR,4 ;all done? NEXT ;no clear next ;yes continue Indirect Addressing 7 0 File Select Register Location Select 1FFh © 2005 Microchip Technology Inc. ...
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... SEGx, COMy, where x and y are segment and common identifiers) are shown as direct connections to the device pins. The signals are outputs from the LCD module and may be tri-stated, depending on the configuration of the LCD module. © 2005 Microchip Technology Inc. EXAMPLE 3-1: BCF STATUS,RP0 BCF STATUS,RP1 CLRF ...
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... TRISA4 TRISA3 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-x R/W-x R/W-x RA2 RA1 RA0 bit Bit is unknown R/W-1 R/W-1 R/W-1 TRISA2 TRISA1 TRISA0 bit Bit is unknown © 2005 Microchip Technology Inc. ...
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... LCD FIGURE 3-1: BLOCK DIAGRAM OF RA0/AN0/C1-/SEG12 Data Bus D WR PORTA CK Data Latch D WR TRISA CK TRIS Latch RD TRISA SEG12 © 2005 Microchip Technology Inc Analog Input or SE12 and LCDEN SE12 and LCDEN RD PORTA SE12 and LCDEN To A/D Converter or Comparator Preliminary PIC16F946 V ...
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... BLOCK DIAGRAM OF RA1/AN1/C2-/SEG7 Data Bus D WR PORTA CK Data Latch D WR TRISA CK TRIS Latch RD TRISA SEG7 DS41265A-page Analog Input or SE7 and LCDEN SE7 and LCDEN RD PORTA SE7 and LCDEN To A/D Converter or Comparator Preliminary V DD I/O Pin TTL Input Buffer © 2005 Microchip Technology Inc. ...
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... LCD FIGURE 3-3: BLOCK DIAGRAM OF RA2/AN2/C2+/V Data Bus D WR PORTA CK Data Latch D WR TRISA CK TRIS Latch RD TRISA COM2 To A/D Converter or Comparator To A/D Module V © 2005 Microchip Technology Inc. -/COM2 REF LCDEN and LMUX<1:0> PORTA LCDEN and LMUX<1:0> Input REF Preliminary PIC16F946 ...
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... Data Latch D WR TRISA CK TRIS Latch RD TRISA SEG15 To A/D Module V DS41265A-page 32 pin is +/SEG15 REF Analog Input or SE15 and LCDEN SE15 and LCDEN RD PORTA SE15 and LCDEN + Input REF Preliminary V DD I/O Pin V SS TTL Input Buffer © 2005 Microchip Technology Inc. ...
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... FIGURE 3-5: BLOCK DIAGRAM OF RA4/C1OUT/T0CKI/SEG4 CM<2:0> = 110 or 101 Data Bus D WR PORTA CK Data Latch D WR TRISA CK TRIS Latch RD TRISA T0CKI SEG4 © 2005 Microchip Technology Inc. C1OUT Analog Input or SE4 and LCDEN SE4 and LCDEN RD PORTA Schmitt Trigger SE4 and LCDEN ...
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... CM<2:0> = 110 or 101 Data Bus D WR PORTA CK Data Latch D WR TRISA CK TRIS Latch RD TRISA To SS Input SEG5 AN4 DS41265A-page 34 C2OUT Analog Input or SE5 and LCDEN SE5 and LCDEN RD PORTA SE5 and LCDEN Preliminary V DD I/O Pin V SS TTL © 2005 Microchip Technology Inc. ...
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... BLOCK DIAGRAM OF RA6/OSC2/CLKO/T1OSO CLKO (F Data Bus PORTA CK Q Data Latch TRISA CK Q TRIS Latch F = 00x, 010 OSC or T1OSCEN RD TRISA RD PORTA © 2005 Microchip Technology Inc. From OSC1 F = 1x1 OSC /4) OSC 00x, 010 OSC or T1OSCEN Input Buffer Preliminary PIC16F946 Oscillator Circuit V DD RA6/OSC2/ ...
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... TRISA1 TRISA0 1111 1111 1111 1111 ANS1 ANS0 1111 1111 1111 1111 CM1 CM0 0000 0000 0000 0000 LMUX1 LMUX0 0001 0011 0001 0011 SE1 SE0 0000 0000 uuuu uuuu SE9 SE8 0000 0000 uuuu uuuu © 2005 Microchip Technology Inc. ...
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... TRISB ; BCF STATUS,RP0 ;Bank 0 BCF STATUS,RP1 ; © 2005 Microchip Technology Inc. 3.3 Additional PORTB Pin Functions RB<7:6> are used as data and clock signals, respectively, for both serial programming and the in-circuit debugger features on the device. Also, RB0 can be configured as an external interrupt input. ...
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... Bit is set ‘0’ = Bit is cleared Preliminary R/W-x R/W-x R/W-x RB2 RB1 RB0 bit Bit is unknown R/W-1 R/W-1 R/W-1 TRISB2 TRISB1 TRISB0 bit Bit is unknown U-0 U-0 U-0 — — — bit Bit is unknown © 2005 Microchip Technology Inc. ...
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... Pull-up disabled Note 1: Global RBPU must be enabled for individual pull-ups to be enabled. 2: The weak pull-up device is automatically disabled if the pin is in Output mode (TRISB<7:0> = 0). Legend Readable bit - n = Value at POR © 2005 Microchip Technology Inc. R/W-1 R/W-1 R/W-1 R/W-1 WPUB5 WPUB4 WPUB3 ...
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... LCD 3.3.3.4 RB3/SEG3 Figure 3-9 shows the diagram for this pin. The RB3/SEG3 pin is configurable to function as one of the following: • a general purpose I/O • an analog output for the LCD DS41265A-page 40 Preliminary © 2005 Microchip Technology Inc. ...
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... TRIS Latch RD TRISB SEG<3:0> (2) INT Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. 2: RB0 only. © 2005 Microchip Technology Inc. SE<3:0> SE<3:0> and LCDEN TTL Input Buffer RD PORTB SE<3:0> and LCDEN SE0 and LCDEN Schmitt ...
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... From other RB<7:4> pins COM0 Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. DS41265A-page 42 LCDEN LCDEN TTL Input Buffer LCDEN LCDEN Preliminary Weak P Pull-up I/O Pin RD PORTB F /4 OSC © 2005 Microchip Technology Inc. ...
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... RD PORTB Set RBIF From other RB<7:4> pins LCDEN and LMUX<1:0> COM1 Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. © 2005 Microchip Technology Inc. LCDEN and LMUX<1:0> 00 LCDEN and LMUX<1:0> 00 TTL Input Buffer Q EN ...
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... To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. DS41265A-page 44 Input Buffer SE14 and LCDEN Q Q Program Mode/ICD Schmitt Trigger Buffer SE14 and LCDEN Preliminary V DD Weak P Pull- I/O Pin TTL PORTB OSC © 2005 Microchip Technology Inc. ...
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... TRIS Latch PGD DRVEN RD TRISB RD PORTB Set RBIF From other RB<7:4> pins SE13 and LCDEN PGD SEG13 Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. © 2005 Microchip Technology Inc. ( Input Buffer SE13 and LCDEN Q Q ...
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... TRISB0 1111 1111 1111 1111 RBIF 0000 000x 0000 000x WPUB0 1111 1111 1111 1111 — — 0000 ---- 0000 ---- LMUX0 0001 0011 0001 0011 SE0 0000 0000 uuuu uuuu SE8 0000 0000 uuuu uuuu © 2005 Microchip Technology Inc. ...
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... TRISC<7:0>: PORTC Tri-State Control bits 1 = PORTC pin configured as an input (tri-stated PORTC pin configured as an output Note: TRISC<7:6> always reads ‘1’ in XT, HS and LP OSC modes. Legend Readable bit - n = Value at POR © 2005 Microchip Technology Inc. EXAMPLE 3-3: BCF STATUS,RP0 ;Bank 0 BCF STATUS,RP1 ; CLRF PORTC BSF STATUS,RP0 ...
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... Figure 3-16 shows the diagram for this pin. The RC2/VLCD3 pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the LCD bias voltage (VLCDEN and LMUX<1:0> 00) (VLCDEN and LMUX<1:0> 00) Preliminary V DD RC0/VLCD1 Pin Schmitt Trigger © 2005 Microchip Technology Inc. ...
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... FIGURE 3-16: BLOCK DIAGRAM OF RC2/VLCD3 Data Bus PORTC CK Q Data Latch TRISC Q CK TRIS Latch RD TRISC RD PORTC VLCD3 © 2005 Microchip Technology Inc. (VLCDEN and LMUX<1:0> 00) (VLCDEN and LMUX<1:0> 00) VLCDEN Schmitt Trigger VLCDEN Preliminary PIC16F946 V DD RC1/VLCD2 Pin Schmitt Trigger V DD ...
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... LCD FIGURE 3-17: BLOCK DIAGRAM OF RC3/SEG6 Data Bus PORTC Q CK Data Latch TRISC Q CK TRIS Latch RD TRISC RD PORTC SEG6 DS41265A-page 50 SE6 and LCDEN Schmitt Trigger SE6 and LCDEN Preliminary V DD RC3/SEG6 Pin © 2005 Microchip Technology Inc. ...
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... BLOCK DIAGRAM OF RC4/T1G/SDO/SEG11 PORT/SDO Select Data Bus PORTC CK Q Data Latch TRISC CK Q TRIS Latch RD TRISC RD PORTC Timer1 Gate SEG11 © 2005 Microchip Technology Inc. SDO 0 1 SE11 and LCDEN SE11 and LCDEN Preliminary PIC16F946 V DD RC4/T1G/ SDO/SEG11 Pin V SS Schmitt ...
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... Select) and CCPMX CCP1 Data Out Data Bus PORTC CK Q Data Latch TRISC CK Q TRIS Latch RD TRISC SE10 and LCDEN RD PORTC Timer1 Gate SEG10 DS41265A-page Schmitt Trigger SE10 and LCDEN Preliminary V DD RC5/T1CKI/ CCP1/SEG10 Pin V SS © 2005 Microchip Technology Inc. ...
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... Drive RD PORTC CK/SCL/SCK Input SEG9 Note 1: If all three data output sources are enabled, the following priority order will be used: • USART data • SSP data • PORT data © 2005 Microchip Technology Inc. ( SE9 and LCDEN SE9 and LCDEN Preliminary ...
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... If SSP and USART outputs are both enabled, the USART data output will have priority over the SSP data output. Both SSP and USART data outputs will have priority over the PORT data output. DS41265A-page SE8 and LCDEN Schmitt Trigger Preliminary V DD RC7/RX/DT/ SDI/SDA/ SEG8 Pin © 2005 Microchip Technology Inc. ...
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... SE15 SE14 Legend unknown unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC. Note 1: This register is only initialized by a POR or BOR and is unchanged by other Resets. © 2005 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 RC5 RC4 RC3 ...
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... U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary INITIALIZING PORTD ;Init PORTD ;Set RD<7:0> as inputs ; R/W-x R/W-x R/W-x RD2 RD1 RD0 bit Bit is unknown R/W-1 R/W-1 R/W-1 TRISD2 TRISD1 TRISD0 bit Bit is unknown © 2005 Microchip Technology Inc. ...
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... Figure 3-25 shows the diagram for this pin. The RD5/SEG18 pin is configurable to function as one of the following: • a general purpose I/O • an analog output for the LCD © 2005 Microchip Technology Inc. 3.5.1.7 RD6/SEG19 Figure 3-25 shows the diagram for this pin. The RD6/SEG19 pin is configurable to function as one of the following: • ...
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... COM3 FIGURE 3-23: BLOCK DIAGRAM OF RD1 Data Bus PORTD CK Q Data Latch TRISD CK Q TRIS Latch RD TRISD RD PORTD DS41265A-page 58 Schmitt Trigger LCDEN and LMUX<1:0> LCDEN and LMUX<1:0> Schmitt Trigger Preliminary V DD RD0/COM3 Pin V DD RD1 Pin © 2005 Microchip Technology Inc. ...
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... FIGURE 3-25: BLOCK DIAGRAM OF RD<7:3> Data Bus PORTD CK Q Data Latch TRISD CK Q TRIS Latch RD TRISD RD PORTD SE<20:16> and LCDEN SEG<20:16> © 2005 Microchip Technology Inc Schmitt Trigger SE<20:16> and LCDEN Schmitt Trigger Preliminary PIC16F946 V DD RD2/CCP2 Pin V DD RD<7:3> Pin DS41265A-page 59 ...
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... SE18 Preliminary Value on all Value on: Bit 1 Bit 0 other POR, BOR Resets RD1 RD0 xxxx xxxx uuuu uuuu CCP2M0 --00 0000 --00 0000 TRISD0 1111 1111 1111 1111 LMUX0 0001 0011 0001 0011 SE17 SE16 0000 0000 uuuu uuuu © 2005 Microchip Technology Inc. ...
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... TRISE<7:4>: Data Direction bits bit 3 TRISE3: Data Direction bit. RE3 is always an input, so this bit always reads as a ‘1’ bit 2-0 TRISE<2:0>: Data Direction bits Legend Readable bit - n = Value at POR © 2005 Microchip Technology Inc. EXAMPLE 3-5: BCF STATUS,RP0 BCF STATUS,RP1 CLRF PORTE ...
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... I/O • an analog output for the LCD 3.6.1.8 RE7/SEG27 Figure 3-26 shows the diagram for this pin. The RE7/SEG27 pin is configurable to function as one of the following: • a general purpose I/O • an analog output for the LCD Preliminary © 2005 Microchip Technology Inc. ...
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... CK Q Data Latch TRISE CK Q TRIS Latch RD TRISE RD PORTE SEG<27:21> (1) AN<7:5> Note 1: Analog input for A/D apply to RE<2:0> pins only. © 2005 Microchip Technology Inc. Analog Mode or Schmitt SE<27:21> and LCDEN Trigger SE<27:21> and LCDEN Preliminary PIC16F946 V DD RE<7:4,2:0> Pins DS41265A-page 63 ...
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... ADON 0000 0000 0000 0000 TRISE1 TRISE0 1111 1111 1111 1111 ANS1 ANS0 1111 1111 1111 1111 LMUX1 LMUX0 0001 0011 0001 0011 SE17 SE16 0000 0000 uuuu uuuu SE25 SE24 0000 0000 uuuu uuuu © 2005 Microchip Technology Inc. ...
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... REGISTER 3-14: TRISF – PORTF TRI-STATE REGISTER (ADDRESS: 185h) R/W-1 R/W-1 TRISF7 TRISF6 bit 7 bit 7-0 TRISF<7:0>: Data Direction bits Legend Readable bit - n = Value at POR © 2005 Microchip Technology Inc. EXAMPLE 3-6: BCF STATUS,RP0 BCF STATUS,RP1 CLRF PORTF BSF STATUS,RP0 BCF STATUS,RP1 ...
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... I/O • an analog output for the LCD 3.7.1.8 RF7/SEG31 Figure 3-28 shows the diagram for this pin. The RF7/SEG31 pin is configurable to function as one of the following: • a general purpose I/O • an analog output for the LCD Preliminary © 2005 Microchip Technology Inc. ...
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... Legend unknown unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTF. Note 1: This register is only initialized by a POR or BOR and is unchanged by other Resets. © 2005 Microchip Technology Inc. Analog Mode or Schmitt SE<31:28, 35:32> and LCDEN Trigger Bit 5 ...
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... Bit is cleared Preliminary INITIALIZING PORTG ;Bank 3 ; ;Init PORTG ;Bank 1 ; ;Set RG<3:0> as inputs ; ;Make RG<2:0> as I/O’s ;Bank 0 ; R/W-x R/W-x R/W-x RG2 RG1 RG0 bit Bit is unknown R/W-1 R/W-1 R/W-1 TRISG2 TRISG1 TRISG0 bit Bit is unknown © 2005 Microchip Technology Inc. ...
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... LCD 3.8.1.6 RG5/SEG41 Figure 3-29 shows the diagram for this pin. The RG5/SEG41 pin is configurable to function as one of the following: • a general purpose I/O • an analog output for the LCD © 2005 Microchip Technology Inc. Preliminary PIC16F946 DS41265A-page 69 ...
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... POR, BOR Resets ADON 0000 0000 0000 0000 ANS1 ANS0 1111 1111 1111 1111 LMUX1 LMUX0 0001 0011 0001 0011 TRISG1 TRISG0 --11 1111 --11 1111 RG1 RG0 --xx xxxx --uu uuuu SE33 SE32 0000 0000 uuuu uuuu SE41 SE40 ---- --00 ---- --uu © 2005 Microchip Technology Inc. ...
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... External Oscillator OSC2 Sleep OSC1 Internal Oscillator HFINTOSC 8 MHz LFINTOSC 31 kHz © 2005 Microchip Technology Inc. The PIC16F946 can be configured in one of eight clock modes – External clock with I/O on RA6 – Low-gain Crystal or Ceramic Resonator Oscillator mode – Medium-gain Crystal or Ceramic Resonator Oscillator mode ...
Page 74
... Value at POR q = value depends on condition DS41265A-page 72 R/W-1 R/W-0 R-q R-0 (1) IRCF1 IRCF0 OSTS HTS W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R-0 R/W-0 LTS SCS bit Bit is unknown © 2005 Microchip Technology Inc. ...
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... PIC16F946. When switching between clock sources a delay is required to allow the new clock to stabilize. These oscillator delays are shown in Table 4-1. © 2005 Microchip Technology Inc. 4.3.1.1 Special Case An exception to this is when the device is put to Sleep while the following conditions are true: • ...
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... POR, an internal delay is invoked to allow the memory bias to stabilize before program execution can begin. LFIOSC 10 s internal delay Following a switch from a LFIOSC or POR, an internal delay is invoked to allow the memory bias to stabilize before program execution can begin. Preliminary Comments © 2005 Microchip Technology Inc. ...
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... CLKIN (External System) FOSC<2:0> = 011 RA6 RA6/OSC2/CLKO/T1OSO © 2005 Microchip Technology Inc. 4.3.3 LP, XT, HS MODES The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to the OSC1 and OSC2 pins (Figures 4-3 and 4-4). The mode selects a low, medium or high gain setting of the internal inverter-amplifier to support various resonator types and speed ...
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... additional parallel feedback resistor (R resonator operation (typical value vary Preliminary CERAMIC RESONATOR OPERATION ( MODE) PIC16F946 OSC1 To Int. Logic (2) ( Sleep OSC2 ( may be required for S varies with the oscillator may be required for proper ceramic P © 2005 Microchip Technology Inc. ...
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... C values. The user also needs to take into account EXT variation due to tolerance of external RC components used. © 2005 Microchip Technology Inc. 4.4 Internal Clock Modes The PIC16F946 has two independent, internal oscillators that can be configured or selected as the system clock source. ...
Page 80
... Monitor (FSCM) and peripherals, are not affected by the change in frequency. U-0 U-0 R/W-0 R/W-0 — — TUN4 TUN3 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 R/W-0 TUN2 TUN1 TUN0 bit Bit is unknown © 2005 Microchip Technology Inc. ...
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... Following any Reset, the IRCF bits are set to ‘110’ and the frequency selection is set to 4 MHz. The user can modify the IRCF bits to select a different frequency. © 2005 Microchip Technology Inc. 4.4.5 HF AND LF INTOSC CLOCK SWITCH TIMING When switching between the LFINTOSC and the HFINTOSC, the new oscillator may already be shut down to save power ...
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... CHECKING EXTERNAL/INTERNAL CLOCK STATUS Checking the state of the OSTS bit (OSCCON<3>) will confirm if the PIC16F946 is running from the external clock source as defined by the FOSC bits in the Configuration Word (CONFIG) or the internal oscillator. Timer are counted. Preliminary © 2005 Microchip Technology Inc. ...
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... OSFIE bit (PIE2<7>) is set. The device will then switch the system clock to the internal oscillator. The system clock will continue to come from the internal oscillator unless the external clock recovers and the Fail-Safe condition is exited. © 2005 Microchip Technology Inc ...
Page 84
... OSTS HTS LTS — TUN4 TUN3 TUN2 TUN1 MCLRE PWRTE WDTE FOSC2 FOSC1 Preliminary Failure Detected CM Test Value on Value on: Bit 0 all other POR, BOR Resets SCS -110 q000 -110 x000 TUN0 ---0 0000 ---u uuuu FOSC0 — — © 2005 Microchip Technology Inc. ...
Page 85
... INTOSC Note: T0SE, T0CS, PSA and PS<2:0> are bits in the Option register; WDTPS<3:0> are bits in the WDTCON register. © 2005 Microchip Technology Inc. Counter mode is selected by setting the T0CS bit (OPTION_REG<5>). In this mode, the Timer0 module will increment either on every rising or falling edge of pin RA4/C1OUT/T0CKI/SEG4 ...
Page 86
... Value at POR DS41265A-page 84 R/W-1 R/W-1 R/W-1 R/W-1 T0CS T0SE PSA ( 128 256 1 : 128 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 PS2 PS1 PS0 bit Bit is unknown © 2005 Microchip Technology Inc. ...
Page 87
... OPTION_REG RBPU INTEDG 85h TRISA TRISA7 TRISA6 Legend: – = Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the Timer0 module. © 2005 Microchip Technology Inc. EXAMPLE 5-1: BCF STATUS,RP0 CLRWDT CLRF TMR0 BSF STATUS,RP0 MOVLW b’00101111’ ...
Page 88
... PIC16F946 NOTES: DS41265A-page 86 Preliminary © 2005 Microchip Technology Inc. ...
Page 89
... CCP1/SEG10 Note 1: Timer1 increments on the rising edge Buffer is low-power type when using LP oscillator or high-speed type when using T1CKI. © 2005 Microchip Technology Inc. The Timer1 Control register (T1CON), shown in Register 6-1, is used to enable/disable Timer1 and select the various features of the Timer1 module. ...
Page 90
... Timer1 gate source. Timer1 gate can be inverted using the T1GINV bit (T1CON<7>), whether it originates from the T1G pin or Comparator 2 output. This configures Timer1 to measure either the active-high or active-low time between events. Preliminary © 2005 Microchip Technology Inc. Register 8-2 for more ...
Page 91
... Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source. 2: T1GE bit must be set to use either T1G pin or C2OUT, as selected by the T1GSS bit (CMCON1<1>), as a Timer1 gate source. Legend Readable bit - n = Value at POR © 2005 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 T1CKPS1 T1CKPS0 T1OSCEN (1) ...
Page 92
... In the event that a write to Timer1 coincides with a special event trigger from CCP1 or CCP2, the write will take precedence. In this mode of operation, the CCPRxH:CCPRxL register pair effectively becomes the period register for Timer1. Preliminary © 2005 Microchip Technology Inc. T1OSCEN = 1 and “special event trigger” ...
Page 93
... T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu 97h CMCON1 — — 8Ch PIE1 EEIE ADIE RCIE Legend unknown unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. © 2005 Microchip Technology Inc. Bit 4 Bit 3 Bit 2 INTE RBIE T0IF TXIF SSPIF CCP1IF TMR2IF — ...
Page 94
... PIC16F946 NOTES: DS41265A-page 92 Preliminary © 2005 Microchip Technology Inc. ...
Page 95
... Legend Readable bit - n = Value at POR © 2005 Microchip Technology Inc. 7.1 Timer2 Operation Timer2 can be used as the PWM time base for the PWM mode of the CCP module. The TMR2 register is readable and writable, and is cleared on any device Reset ...
Page 96
... Value on Value on Bit 1 Bit 0 all other POR, BOR Resets INTF RBIF 0000 000x 0000 000x TMR2IF TMR1IF 0000 0000 0000 0000 0000 0000 0000 0000 TMR2IE TMR1IE 0000 0000 0000 0000 1111 1111 1111 1111 © 2005 Microchip Technology Inc. ...
Page 97
... The corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. Legend Readable bit - n = Value at POR © 2005 Microchip Technology Inc. The CMCON0 register (Register 8-1) controls the comparator input and output multiplexers. A block two analog diagram of the various comparator configurations is shown in Figure 8-3 ...
Page 98
... Any external component 1 connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage 0.6V T Leakage V = 0.6V T ±500 nA Vss Preliminary SINGLE COMPARATOR + Output – © 2005 Microchip Technology Inc. ...
Page 99
... CIS = 1 COM2 Internal 0.6V reference Legend Analog Input, port reads zeros always. © 2005 Microchip Technology Inc. If the Comparator mode is changed, the comparator output level may not be valid for the specified mode change delay shown in Section 19.0 “Electrical Specifications”. Note: Comparator interrupts should be disabled during a Comparator mode change ...
Page 100
... FIGURE 8-5: COMPARATOR C2 OUTPUT BLOCK DIAGRAM C2SYNC To TMR1 To C2OUT pin To Data Bus RD CMCON Set C2IF bit Note 1: Comparator 2 output is latched on falling edge of T1 clock source. DS41265A-page NReset TMR1 EN Clock Source Reset Preliminary C1INV RD CMCON C2INV (1) RD CMCON © 2005 Microchip Technology Inc. ...
Page 101
... Diagram for more information recommended to synchronize Comparator 2 with Timer1 by setting the C2SYNC bit when Comparator 2 is used as the Timer1 gate source. This ensures Timer1 does not miss an increment if Comparator 2 changes during an increment. © 2005 Microchip Technology Inc. U-0 U-0 U-0 U-0 — ...
Page 102
... Section 19.0 “Electrical Specifications”. DD /32 Stages REN VR <3:0> = ‘0000’ Preliminary to V cannot be realized due from approaching V or REF SS when VR<3:0> = 0000. SS module current. REF derived and therefore, the DD . The DD VRR 8R © 2005 Microchip Technology Inc. ...
Page 103
... If the device wakes up from Sleep, the contents of the CMCON0, CMCON1 and VRCON registers are not affected. © 2005 Microchip Technology Inc. 8.9 Effects of a Reset A device Reset forces the CMCON0, CMCON1 and VRCON registers to their Reset states ...
Page 104
... RBIF 0000 000x 0000 000x — CCP2IF 0000 -0-0 0000 -0-0 CM1 CM0 0000 0000 0000 0000 C2SYNC ---- --10 ---- --10 TRISA0 1111 1111 1111 1111 — CCP2IE 0000 -0-0 0000 -0-0 VR1 VR0 0-0- 0000 0-0- 0000 © 2005 Microchip Technology Inc. ...
Page 105
... SE<23:16> • LCDSE3 SE<31:24> • LCDSE4 SE<39:32> • LCDSE5 SE<41:40> example, LCDSEn is detailed in Register 9-3. © 2005 Microchip Technology Inc. Once the module is initialized for the LCD panel, the individual bits of the LCDDATA<11:0> registers are cleared/set to represent respectively: • LCDDATA0 SEG7COM0:SEG0COM0 • ...
Page 106
... These signals are connected directly to the I/O pads, but may be tri-stated, depending on the configuration of the LCD module. DS41265A-page 104 168 LCDDATAx SEG<42:0> to Registers 24) MUX LCDCON COM<3:0> LCDPS To I/O Pads LCDSEn Select and Prescaler Preliminary (1) To I/O Pads (1) © 2005 Microchip Technology Inc. ...
Page 107
... OSC 01 = T1OSC (Timer1)/ LFINTOSC (31 kHz)/32 bit 1-0 LMUX<1:0>: Commons Select bits LMUX<1:0> Legend Readable bit C = Only clearable bit - n = Value at POR © 2005 Microchip Technology Inc. R/C-0 R/W-1 R/W-0 WERR VLCDEN CS1 Multiplex Maximum Number of Pixels Static (COM0) 42 1/2 (COM<1:0>) 84 1/3 (COM<2:0>) 126 1/4 (COM< ...
Page 108
... R = Readable bit - n = Value at POR DS41265A-page 106 R-0 R-0 R/W-0 R/W-0 LCDA WA LP3 LP2 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary © 2005 Microchip Technology Inc. R/W-0 R/W-0 LP1 LP0 bit Bit is unknown ...
Page 109
... COMy COMy bit 7 bit 7-0 SEGx-COMy: Pixel On bits 1 = Pixel on (dark Pixel off (clear) Legend Readable bit - n = Value at POR © 2005 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 SEn SEn SEn SEn W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘ ...
Page 110
... V 1 LCD Driver ( LCD LCD LCD Bias 1 Connections for External R-ladder Static Bias 1/2 Bias 1/3 Bias Preliminary and 1/2 V and 1 2 The Bias Static 1/2 Bias 1/3 Bias Bias — 1 — 1 © 2005 Microchip Technology Inc. ...
Page 111
... Any LCD pixel location not being used for display can be used as general purpose RAM. 9.6 LCD Frame Frequency The rate at which the COM and SEG outputs change is called the LCD frame frequency. © 2005 Microchip Technology Inc. TABLE 9-2: Multiplex Static 1/2 1/3 ...
Page 112
... LCD CLOCK GENERATION F OSC ÷8192 T1OSC 32 kHz ÷32 Crystal Osc. LFINTOSC ÷32 Nom kHz RC CS<1:0> (LCDCON<3:2>) DS41265A-page 110 STAT ÷4 DUP ÷2 4-bit Prog Presc TRIP QUAD LP<3:0> (LCDPS<3:0>) LMUX<1:0> (LCDCON<1:0>) Preliminary © 2005 Microchip Technology Inc. ÷ Ring Counter LMUX<1:0> (LCDCON<1:0>) ...
Page 113
... FIGURE 9-4: LCD SEGMENT MAPPING WORKSHEET (PART © 2005 Microchip Technology Inc. Preliminary PIC16F946 DS41265A-page 111 ...
Page 114
... PIC16F946 FIGURE 9-5: LCD SEGMENT MAPPING WORKSHEET (PART DS41265A-page 112 Preliminary © 2005 Microchip Technology Inc. ...
Page 115
... FIGURE 9-6: TYPE-A/TYPE-B WAVEFORMS IN STATIC DRIVE COM0 COM0-SEG0 COM0-SEG1 © 2005 Microchip Technology Inc. The LCDs can be driven by two types of waveform: Type-A and Type-B. In Type-A waveform, the phase changes within each common type, whereas in Type-B waveform, the phase changes on each frame boundary. Thus, Type-A waveform maintains ‘ ...
Page 116
... PIC16F946 FIGURE 9-7: TYPE-A WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE COM1 COM0 COM0-SEG0 COM0-SEG1 DS41265A-page 114 COM0 COM1 SEG0 SEG1 1 Frame Preliminary © 2005 Microchip Technology Inc. ...
Page 117
... FIGURE 9-8: TYPE-B WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE COM1 COM0 COM0-SEG0 COM0-SEG1 © 2005 Microchip Technology Inc. COM0 COM1 SEG0 SEG1 2 Frames Preliminary PIC16F946 DS41265A-page 115 ...
Page 118
... PIC16F946 FIGURE 9-9: TYPE-A WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE COM1 COM0 COM0-SEG0 COM0-SEG1 DS41265A-page 116 COM0 COM1 SEG0 SEG1 1 Frame Preliminary © 2005 Microchip Technology Inc. ...
Page 119
... FIGURE 9-10: TYPE-B WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE COM1 COM0 COM0-SEG0 COM0-SEG1 © 2005 Microchip Technology Inc. COM0 COM1 SEG0 SEG1 2 Frames Preliminary PIC16F946 DS41265A-page 117 ...
Page 120
... PIC16F946 FIGURE 9-11: TYPE-A WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE COM2 COM1 COM0 COM0-SEG0 COM0-SEG1 DS41265A-page 118 COM0 COM1 COM2 SEG0 SEG2 SEG1 Preliminary Frame © 2005 Microchip Technology Inc. ...
Page 121
... FIGURE 9-12: TYPE-B WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE COM2 COM1 COM0 COM0-SEG0 COM0-SEG1 © 2005 Microchip Technology Inc. COM0 COM1 COM2 SEG0 SEG1 Preliminary PIC16F946 Frames DS41265A-page 119 ...
Page 122
... PIC16F946 FIGURE 9-13: TYPE-A WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE COM2 COM1 COM0 COM0-SEG0 COM0-SEG1 DS41265A-page 120 COM0 COM1 COM2 SEG0 SEG2 SEG1 Preliminary Frame © 2005 Microchip Technology Inc. ...
Page 123
... FIGURE 9-14: TYPE-B WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE COM2 COM1 COM0 COM0-SEG0 COM0-SEG1 © 2005 Microchip Technology Inc. COM0 COM1 COM2 SEG0 SEG1 Preliminary PIC16F946 Frames DS41265A-page 121 ...
Page 124
... PIC16F946 FIGURE 9-15: TYPE-A WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE COM3 COM2 COM1 COM0 COM0-SEG0 COM0-SEG1 DS41265A-page 122 COM0 COM1 COM2 COM3 SEG0 SEG1 1 Frame Preliminary © 2005 Microchip Technology Inc. ...
Page 125
... FIGURE 9-16: TYPE-B WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE COM3 COM2 COM1 COM0 COM0-SEG0 COM0-SEG1 © 2005 Microchip Technology Inc. COM0 COM1 COM2 COM3 SEG0 SEG1 2 Frames Preliminary PIC16F946 DS41265A-page 123 ...
Page 126
... Type-A waveform is selected and when the Type-B with no multiplex (static) is selected. LCD Interrupt Occurs 2 Frames T FWR Frame Boundary /2 CY minimum = 1.5(T /4) – ns) FRAME CY maximum = 1.5(T /4) – ns) FRAME CY Preliminary Controller Accesses Next Frame Data FINT Frame Boundary © 2005 Microchip Technology Inc. ...
Page 127
... TABLE 9-4: LCD MODULE STATUS DURING SLEEP Clock Source SLPEN During Sleep? 0 T1OSC 1 0 LFINTOSC OSC 1 Note: The LFINTOSC or external T1OSC oscillator must be used to operate the LCD module during Sleep. © 2005 Microchip Technology Inc. Operation Yes No Yes Preliminary PIC16F946 DS41265A-page 125 ...
Page 128
... PIC16F946 FIGURE 9-18: SLEEP ENTRY/EXIT WHEN SLPEN = 1 OR CS<1:0> COM0 COM1 COM2 SEG0 2 Frames SLEEP Instruction Execution DS41265A-page 126 Wake-up Preliminary © 2005 Microchip Technology Inc ...
Page 129
... LCDDATA0 through LCDDATA11. 5. Clear LCD Interrupt Flag, LCDIF (PIR2<4>) and if desired, enable the interrupt by setting bit LCDIE (PIE2<4>). 6. Enable bias voltage pins (VLCD<3:1>) by setting VLCDEN (LCDCON<4>). 7. Enable the LCD module by setting bit LCDEN (LCDCON<7>). © 2005 Microchip Technology Inc. Preliminary PIC16F946 DS41265A-page 127 ...
Page 130
... COM0 SEG40 ---- --xx ---- --uu COM0 SEG24 xxxx xxxx uuuu uuuu COM1 SEG32 xxxx xxxx uuuu uuuu COM1 SEG40 ---- --xx ---- --uu COM1 SEG24 xxxx xxxx uuuu uuuu COM2 SEG32 xxxx xxxx uuuu uuuu COM2 SEG40 ---- --xx ---- --uu COM2 © 2005 Microchip Technology Inc. ...
Page 131
... Shaded cells are not used by the LCD module. Note 1: These pins may be configured as port pins, depending on the oscillator mode selected. 2: This register is only initialized by a POR or BOR and is unchanged by other Resets. © 2005 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 ...
Page 132
... PIC16F946 NOTES: DS41265A-page 130 Preliminary © 2005 Microchip Technology Inc. ...
Page 133
... Not tested and below minimum V Legend Readable bit - n = Value at POR © 2005 Microchip Technology Inc. 10.1.1 PLVD CALIBRATION The PIC16F91X stores the PLVD calibration values in fuses located in the Calibration Word 2 (2009h). The Calibration Word 2 is not erased when using the spec- ified bulk erase sequence in the “ ...
Page 134
... LCDIE — LVDIE — IRVST LVDEN — LVDL2 LVDL1 Preliminary Value on Value on Bit 0 all other POR, BOR Resets RBIF 0000 000x 0000 000x CCP2IF 0000 -0-0 0000 -0-0 CCP2IE 0000 -0-0 0000 -0-0 LVDL0 --00 -100 --00 -100 © 2005 Microchip Technology Inc. ...
Page 135
... TX9D: 9th bit of Transmit Data, can be Parity bit Legend Readable bit - n = Value at POR © 2005 Microchip Technology Inc. The USART can be configured in the following modes: • Asynchronous (full-duplex) • Synchronous – Master (half-duplex) • Synchronous – Slave (half-duplex) Bit SPEN (RCSTA<7>) and bits TRISC<7:6> have to be ...
Page 136
... Value at POR DS41265A-page 134 R/W-0 R/W-0 R/W-0 RX9 SREN CREN ADDEN W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R-0 R-0 R-x FERR OERR RX9D bit Bit is unknown © 2005 Microchip Technology Inc. ...
Page 137
... SPBRG Baud Rate Generator Register Legend unknown, – = unimplemented, read as ‘0’. Shaded cells are not used by the BRG. © 2005 Microchip Technology Inc. It may be advantageous to use the high baud rate (BRGH = 1) even for slower baud clocks. This is because the F baud rate error in some cases ...
Page 138
... Preliminary = 10 MHz SPBRG % value (decimal) — — 129 — 255 — MHz SPBRG % value (decimal) — — — — 1.71 255 0.16 64 1.72 31 1.36 21 2. 255 - 0 © 2005 Microchip Technology Inc. ...
Page 139
... Note 1: The TSR register is not mapped in data memory not available to the user. 2: Flag bit TXIF is set when enable bit TXEN is set. TXIF is cleared by loading TXREG. © 2005 Microchip Technology Inc. Transmission is enabled by setting enable bit, TXEN (TXSTA<5>). The actual transmission will not occur until standard ...
Page 140
... Pin Buffer 0 and Control TSR Register TRMT TX9 TX9D bit 0 bit 1 bit 7/8 Word 1 bit 0 bit 1 bit 7/8 Word 1 Word 2 Transmit Shift Reg. Preliminary RC6/TX/CK/SCK/ SCL/SEG9 pin SPEN Stop bit Start bit bit 0 Stop bit Word 2 © 2005 Microchip Technology Inc. ...
Page 141
... ADIE 98h TXSTA CSRC TX9 99h SPBRG Baud Rate Generator Register Legend unknown, – = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission. © 2005 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 T0IE INTE RBIE T0IF ...
Page 142
... Read the 8-bit received data by reading the RCREG register any error occurred, clear the error by clearing enable bit CREN. 10. If using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set. Preliminary © 2005 Microchip Technology Inc. ...
Page 143
... EEIE ADIE 98h TXSTA CSRC TX9 99h SPBRG Baud Rate Generator Register Legend unknown, – = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception. © 2005 Microchip Technology Inc. OERR CREN 64 MSb or 16 Stop (8) 7 Data RX9 ...
Page 144
... CPU. OERR CREN 64 RSR Register MSb or 16 Stop (8) 7 Data RX9 Recovery Enable Load of Receive Buffer RX9D RCREG Register 8 RCIF Interrupt RCIE Preliminary FERR LSb Start FIFO Data Bus © 2005 Microchip Technology Inc. ...
Page 145
... TXSTA CSRC TX9 99h SPBRG Baud Rate Generator Register Legend unknown, – = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception. © 2005 Microchip Technology Inc. Start bit 8 Stop bit bit 0 bit 8 bit bit Address Byte ...
Page 146
... Enable the transmission by setting bit TXEN 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. 7. Start transmission by loading data to the TXREG register using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set. Preliminary © 2005 Microchip Technology Inc. ...
Page 147
... Note: Sync Master mode; SPBRG = 0. Continuous transmission of two 8-bit words. FIGURE 11-10: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX/DT/SDI/SDA/SEG8 RC6/TX/CK/SCK/SCL/SEG9 Write to TXREG Reg TXIF bit TRMT bit TXEN bit © 2005 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 T0IE INTE RBIE T0IF ...
Page 148
... SYNC — BRGH TRMT Preliminary Value on Value on: Bit 0 all other POR, BOR Resets RBIF 0000 000x 0000 000x RX9D 0000 000x 0000 000x 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 © 2005 Microchip Technology Inc. ...
Page 149
... TSR and flag bit TXIF will now be set enable bit TXIE is set, the interrupt will wake the chip from Sleep and if the global interrupt is enabled, the program will branch to the interrupt vector (0004h). © 2005 Microchip Technology Inc. Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4 bit 1 bit 2 bit 3 bit 4 ...
Page 150
... Value on Value on: Bit 0 all other POR, BOR Resets RBIF 0000 000x 0000 000x RX9D 0000 000x 0000 000x 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 © 2005 Microchip Technology Inc. ...
Page 151
... Figure 12-1 shows the block diagram of the REF A/D on the PIC16F946. FIGURE 12-1: A/D BLOCK DIAGRAM RA0/AN0/C1-/SEG12 RA1/AN1/C2-/SEG7 RA2/AN2/C2+/V -/COM2 REF RA3/AN3/C1+/V +/SEG15 REF RA5/AN4/C2OUT/SS/SEG5 RE0/AN5/SEG21 RE1/AN6/SEG22 RE2/AN7/SEG23 CHS<2:0> © 2005 Microchip Technology Inc VCFG0 = VCFG0 = 1 REF A/D GO/DONE ADFM ADON V SS VCFG1 = VCFG1 = 1 ...
Page 152
... V > 3.0V time. AD Preliminary . The source calculations for AD 4 MHz 1.25 MHz (2) 500 ns 1.6 s (2) 1.0 s 3.2 s 2.0 s 6.4 s (3) 4.0 s 12.8 s (3) (3) 8.0 s 25.6 s (3) (3) 16.0 s 51.2 s (1,4) (1,4) 2-6 s 2-6 s © 2005 Microchip Technology Inc. ...
Page 153
... The A/D conversion can be supplied in two formats: left or right shifted. The ADFM bit (ADCON0<7>) controls the output format. Figure 12-3 shows the output formats. FIGURE 12-3: 10-BIT A/D RESULT FORMAT (ADFM = 0) MSB bit 7 (ADFM = 1) bit 7 Unimplemented: Read as ‘0’ © 2005 Microchip Technology Inc. Instead, the CYCLES ...
Page 154
... VCFG0 CHS2 CHS1 CHS0 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 R/W-1 ANS2 ANS1 ANS0 bit Bit is unknown R/W-0 R/W-0 GO/DONE ADON bit Bit is unknown © 2005 Microchip Technology Inc. ...
Page 155
... OSC 110 = F /64 OSC bit 3-0 Unimplemented: Read as ‘0’ Legend Readable bit - n = Value at POR © 2005 Microchip Technology Inc. R/W-0 R/W-0 U-0 U-0 ADCS1 ADCS0 — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared ...
Page 156
... MOVWF RESULTLO is AD Preliminary A/D CONVERSION ;Bank 1 ;A/D RC clock ;Set RA0 to input ;Set RA0 to analog ;Bank 0 ;Right, Vdd Vref, AN0 ;Wait min sample time ;Start conversion ;Is conversion done? ;No, test again ;Read upper 2 bits ;Bank 1 ;Read lower 8 bits © 2005 Microchip Technology Inc. ...
Page 157
... The charge holding capacitor (C 3: The maximum recommended impedance for analog sources This is required to meet the pin leakage specification. © 2005 Microchip Technology Inc. As the impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (changed), this acquisition must be done before the conversion can be started ...
Page 158
... A/D module is turned off. The ADON bit remains set. Full-Scale Range 1 LSB Ideal 1/2 LSB Ideal Full-Scale Transition 1/2 LSB Ideal Zero-Scale Transition Preliminary SS C HOLD = DAC capacitance = Sampling Switch (k ) Center of Full-Scale Code Analog Input © 2005 Microchip Technology Inc. ...
Page 159
... Least Significant 2 bits of the left justified A/D result or 8 bits of the right justified result 9Fh ADCON1 — ADCS2 ADCS1 Legend unknown unchanged, – = unimplemented read as ‘0’. Shaded cells are not used for A/D module. © 2005 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 RA5 RA4 RA3 ...
Page 160
... PIC16F946 NOTES: DS41265A-page 158 Preliminary © 2005 Microchip Technology Inc. ...
Page 161
... Additional information on the data EEPROM is ® available in the “PICmicro Mid-Range MCU Family Reference Manual” (DS33023). © 2005 Microchip Technology Inc. 13.1 EEADRL and EEADRH Registers The EEADRL and EEADRH registers can address maximum of 256 bytes of data EEPROM maximum of 8k words of program EEPROM. ...
Page 162
... R/W-0 R/W-0 R/W-0 EEDATL2 EEDATL1 EEDATL0 bit Bit is unknown R/W-0 R/W-0 R/W-0 EEADRL2 EEADRL1 EEADRL0 bit Bit is unknown R/W-0 R/W-0 R/W-0 EEDATH2 EEDATH1 EEDATH0 bit Bit is unknown R/W-0 R/W-0 R/W-0 EEADRH2 EEADRH1 EEADRH0 bit Bit is unknown © 2005 Microchip Technology Inc. ...
Page 163
... RD: Read Control bit 1 = Initiates a memory read (RD is cleared in hardware. The RD bit can only be set, not cleared, in software Does not initiate an memory read Legend Bit can only be set R = Readable bit - n = Value at POR © 2005 Microchip Technology Inc. U-0 U-0 U-0 R/W-x — — — ...
Page 164
... EECON1,WREN ;Enable writes BCF INTCON,GIE MOVLW 55h MOVWF EECON2 MOVLW AAh MOVWF EECON2 BSF EECON1,WR BSF INTCON,GIE BCF EECON1,WREN ;Disable writes Preliminary © 2005 Microchip Technology Inc. ; ;Wait for write ;to complete ;Bank 2 ;Address to write ;to write ;Bank 3 ;memory ;Disable INTs. ; ;Write 55h ; ;Write AAh ...
Page 165
... NOP NOP ; BCF STATUS, RP0 MOVF EEDATA, W MOVWF DATAL MOVF EEDATH, W MOVWF DATAH © 2005 Microchip Technology Inc. bit RD on the next ; ; Bank Byte of Program Address to read ; LS Byte of Program Address to read ; Bank 3 ; Point to PROGRAM memory ; EE Read ; Any instructions here are ignored as program ...
Page 166
... POR, BOR Resets INTF RBIF 0000 000x 0000 000x TMR2IF TMR1IF 0000 0000 0000 0000 TMR2IE TMR1IE 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 --00 0000 --00 0000 ---0 0000 WR RD 0--- x000 ---- q000 ---- ---- ---- ---- © 2005 Microchip Technology Inc. ...
Page 167
... Slave mode (SCK is the clock input) • Clock Polarity (Idle state of SCK) • Clock edge (output data on rising/falling edge of SCK) • Clock Rate (Master mode only) • Slave Select mode (Slave mode only) © 2005 Microchip Technology Inc. ® ® Preliminary PIC16F946 DS41265A-page 165 ...
Page 168
... Value at POR DS41265A-page 166 R-0 R-0 R-0 CKE D ode only mode only mode only modes Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R-0 R-0 R-0 R bit Bit is unknown © 2005 Microchip Technology Inc. ...
Page 169
... Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1111 = Slave mode, 10-bit address with Start and Stop bit interrupts enabled Legend Readable bit - n = Value at POR © 2005 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 R/W-0 SSPEN CKP SSPM3 SSPM2 ...
Page 170
... PORTC). If read-modify-write instructions, such as BSF, are performed on the TRISC register while the SS pin is high, this will cause the TRISC<4> bit to be set, thus disabling the SDO output. TMR2 Output 2 T Prescaler CY 4, 16, 64 Preliminary . DD “DC Characteristics: © 2005 Microchip Technology Inc. ...
Page 171
... TXDATA MOVWF SSPBUF ;New data to xmit © 2005 Microchip Technology Inc. When the application software is expecting to receive valid data, the SSPBUF should be read before the next byte of data to transfer is written to the SSPBUF. Buffer Full bit, BF (SSPSTAT<0>), indicates when SSPBUF has been loaded with the received data (transmission is complete) ...
Page 172
... Master sends data – Slave sends data • Master sends dummy data – Slave sends data SPI™ Slave SSPM<3:0> = 010xb SDO SDI Serial Input Buffer SDI SDO Shift Register MSb Serial Clock SCK SCK Preliminary (SSPBUF) (SSPSR) LSb Processor 2 © 2005 Microchip Technology Inc. ...
Page 173
... Input Sample (SMP = 1) SSPIF SSPSR to SSPBUF © 2005 Microchip Technology Inc. Figure 14-3, Figure 14-5 and Figure 14-6, where the MSB is transmitted first. In Master mode, the SPI clock rate (bit rate) is user programmable to be one of the following: • ( OSC CY • ...
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... SDO pin can be configured as an input. This disables transmissions from the SDO. The SDI can always be left as an input (SDI function) since it cannot create a bus conflict. bit 6 bit 7 bit 7 Preliminary . DD bit 0 bit 0 Next Q4 Cycle after Q2 © 2005 Microchip Technology Inc. ...
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... SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO bit 7 SDI (SMP = 0) bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF © 2005 Microchip Technology Inc. bit 6 bit 5 bit 4 bit 2 bit 3 bit 6 bit 2 bit 5 bit 4 bit 3 Preliminary PIC16F946 bit 1 bit 0 bit 0 Next Q4 Cycle after Q2 ...
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... TMR1IF 0000 0000 0000 0000 xxxx xxxx uuuu uuuu SSPM0 0000 0000 0000 0000 1111 1111 1111 1111 TRISC0 TMR1IE 0000 0000 0000 0000 1111 1111 1111 1111 TRISA0 BF 0000 0000 0000 0000 © 2005 Microchip Technology Inc. ...
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... SSP Status Register (SSPSTAT) • Serial Receive/Transmit Buffer (SSPBUF) • SSP Shift Register (SSPSR) – Not directly accessible • SSP Address Register (SSPADD) © 2005 Microchip Technology Inc. The SSPCON register allows control of the I operation. Four mode selection bits (SSPCON<3:0>) allow one of the following I 2 • ...
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... Receive first (high) byte of address (bits SSPIF and BF are set). 9. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Generate ACK SSPBUF Pulse Yes Yes Preliminary Set bit SSPIF (SSP Interrupt occurs if enabled) Yes Yes Yes Yes © 2005 Microchip Technology Inc. ...
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... Flag bit SSPIF (PIR1<3>) must be cleared in software. The SSPSTAT register is used to determine the status of the byte. 2 FIGURE 14-8: I C™ WAVEFORMS FOR RECEPTION (7-BIT ADDRESS) R Receiving Address SDA SCL S SSPIF (PIR1<3>) BF (SSPSTAT<0>) SSPOV (SSPCON<6>) © 2005 Microchip Technology Inc. Receiving Data ACK ACK ...
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... PIC16F946 2 FIGURE 14-9: I C™ SLAVE MODE TIMING (RECEPTION, 10-BIT ADDRESS) DS41265A-page 178 Preliminary © 2005 Microchip Technology Inc. ...
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... SSPIF (PIR1<3>) BF (SSPSTAT<0>) CKP (SSPCON<4>) © 2005 Microchip Technology Inc. An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF must be cleared in software, and the SSPSTAT register is used to determine the status of the byte. Flag bit SSPIF is set on the falling edge of the ninth clock pulse ...
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... PIC16F946 2 I FIGURE 14-11: C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) DS41265A-page 180 Preliminary © 2005 Microchip Technology Inc. ...
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... Slave mode idle (SSPM<3:0> = 1011), or with the Slave active. When both Master and Slave modes are enabled, the software needs to differentiate the source(s) of the interrupt. © 2005 Microchip Technology Inc. 14.14 Multi-Master Mode In Multi-Master mode, the interrupt generation on the detection of the Start and Stop conditions, allows the determination of when the bus is free ...
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... C™ mode) Address Register D R mode. Preliminary DX-1 Value on: Value on Bit 0 POR, all other BOR Resets RBIF 0000 000x 0000 000x xxxx xxxx uuuu uuuu 1111 1111 1111 1111 0000 0000 0000 0000 BF 0000 0000 0000 0000 © 2005 Microchip Technology Inc. ...
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... PWM Capture None PWM Compare None © 2005 Microchip Technology Inc. CCP2 Module: Capture/Compare/PWM Register2 (CCPR2) is com- prised of two 8-bit registers: CCPR2L (low byte) and CCPR2H (high byte). The CCP2CON register controls the operation of CCP2. The special event trigger is generated by a compare match and will reset Timer1 and start an A/D conversion (if the A/D module is enabled) ...
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... REGISTER (ADDRESS: 17h/1Dh) U-0 R/W-0 R/W-0 R/W-0 — CCPxX CCPxY CCPxM3 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 R/W-0 CCPxM2 CCPxM1 CCPxM0 bit Bit is unknown © 2005 Microchip Technology Inc. ...
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... The user should keep bit CCP1IE (PIE1<2>) clear to avoid false interrupts and should clear the flag bit CCP1IF, following any such change in Operating mode. © 2005 Microchip Technology Inc. 15.1.4 CCP PRESCALER There are four prescaler settings, specified by bits CCP1M< ...
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... This is not the PORTC I/O data latch. Figure 15-5 shows a simplified block diagram of the CCP module in PWM mode. For a step-by-step procedure on how to set up the CCP module for PWM operation, see Section 15.3.3 “Setup for PWM Operation”. Preliminary © 2005 Microchip Technology Inc. ...
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... PWM period = (PR2 • 4 • T (TMR2 prescale value) PWM frequency is defined as 1/[PWM period]. © 2005 Microchip Technology Inc. When TMR2 is equal to PR2, the following three events occur on the next increment cycle: • TMR2 is cleared • The RC5/T1CKI/CCP1/SEG10 pin is set ...
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... CCP2IE 0000 -0-0 0000 -0-0 TRISC1 TRISC0 1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu © 2005 Microchip Technology Inc. ...
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... Capture/Compare/PWM Register 2 (LSB) 1Ch CCPR2H Capture/Compare/PWM Register 2 (MSB) 1Dh CCP2CON — — Legend unknown unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by PWM and Timer2. © 2005 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 T0IE INTE RBIE T0IF RCIF ...
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... PIC16F946 NOTES: DS41265A-page 190 Preliminary © 2005 Microchip Technology Inc. ...
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... Sleep • Code Protection • ID Locations • In-Circuit Serial Programming™ © 2005 Microchip Technology Inc. The PIC16F946 has two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable. The other is the ...
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... BOREN0 CPD CP MCLRE PWRTE (1) ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary configuration memory space during programming. See (DS41244) for more WDTE FOSC2 FOSC1 FOSC0 bit Bit is unknown © 2005 Microchip Technology Inc. ...
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... Ripple Counter LFINTOSC Note 1: Refer to the Configuration Word register (Register 16-1). © 2005 Microchip Technology Inc. They are not affected by a WDT wake-up since this is viewed as the resumption of normal operation. TO and PD bits are set or cleared differently in different Reset situations, as indicated in Table 16-2. These bits are used in software to determine the nature of the Reset ...
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... The Power-up Timer delay will vary from chip-to-chip and vary due to: • V variation DD • Temperature variation • Process variation See DC parameters “Electrical Specifications”). and an internal Preliminary RECOMMENDED MCLR CIRCUIT PIC16F946 or greater) MCLR to rise to an acceptable level. A config- for details (Section 19.0 © 2005 Microchip Technology Inc. ...
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... DD Internal Reset V DD Internal Reset Note delay only if PWRTE bit is programmed to ‘0’. © 2005 Microchip Technology Inc. This will occur regardless of V not insured to occur than parameter (T ). BOR On any Reset (Power-on, Brown-out, Watchdog Timer, etc.), the chip will remain in Reset until V V (see Figure 16-3) ...
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... Z DC — SBOREN — — POR Preliminary may have DD Wake-up from Sleep PWRTE = 1 1024 • T 1024 • T OSC OSC — — Value on Value on Bit 0 all other POR, BOR (1) Resets C 0001 1xxx 000q quuu BOR --01 --qq --0u --uu © 2005 Microchip Technology Inc. ...
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... V DD MCLR Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 16-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH MCLR Internal POR PWRT Time-out OST Time-out Internal Reset © 2005 Microchip Technology Inc. T PWRT T OST T PWRT T OST DD T PWRT T OST Preliminary PIC16F946 ): CASE 3 ...
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... Microchip Technology Inc. ...