PIC16F946T-I/PT Microchip Technology, PIC16F946T-I/PT Datasheet - Page 178

• Manufacturer Part Number: PIC16F946T-I/PT
• Description: Microcontroller
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F946T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 336 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA160011 - DAUGHTER BOARD PICDEM LCD 16F91X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC16F946
14.12.1
Once the SSP module has been enabled, it waits for a
Start condition to occur. Following the Start condition,
the 8-bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
a)
b)
c)
d)
In 10-bit Address mode, two address bytes need to be
received by the slave (Figure 14-8). The five Most
Significant bits (MSbs) of the first address byte specify
if this is a 10-bit address. Bit R/W (SSPSTAT<2>) must
specify a write so the slave device will receive the
second address byte. For a 10-bit address, the first
byte would equal ‘1111 0 A9 A8 0’, where A9 and
A8 are the two MSbs of the address.
TABLE 14-3:
DS41265A-page 176
Note:
Transfer is Received
Status Bits as Data
The SSPSR register value is loaded into the
SSPBUF register.
The Buffer Full bit, BF is set.
An ACK pulse is generated.
SSP Interrupt Flag bit, SSPIF (PIR1<3>) is set
(interrupt is generated if enabled) on the falling
edge of the ninth SCL pulse.
BF
0
1
1
0
ADDRESSING
Shaded cells show the conditions where the user software did not properly clear the overflow condition.
SSPOV
DATA TRANSFER RECEIVED BYTE ACTIONS
0
0
1
1
SSPSR
Yes
No
No
No
SSPBUF
Preliminary
The sequence of events for 10-bit address is as follows,
with steps 7-9 for slave-transmitter:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Generate ACK
Receive first (high) byte of address (bits SSPIF,
BF and bit UA (SSPSTAT<1>) are set).
Update the SSPADD register with second (low)
byte of address (clears bit UA and releases the
SCL line).
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Receive second (low) byte of address (bits
SSPIF, BF and UA are set).
Update the SSPADD register with the first (high)
byte of address; if match releases SCL line, this
will clear bit UA.
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Receive repeated Start condition.
Receive first (high) byte of address (bits SSPIF
and BF are set).
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Pulse
Yes
No
No
No
© 2005 Microchip Technology Inc.
(SSP Interrupt occurs
Set bit SSPIF
if enabled)
Yes
Yes
Yes
Yes