PIC16F946T-I/PT Microchip Technology, PIC16F946T-I/PT Datasheet - Page 172

• Manufacturer Part Number: PIC16F946T-I/PT
• Description: Microcontroller
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F946T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 336 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA160011 - DAUGHTER BOARD PICDEM LCD 16F91X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC16F946
14.3
To enable the serial port, SSP Enable bit, SSPEN
(SSPCON<5>), must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, re-initialize the
SSPCON registers and then set the SSPEN bit. This
configures the SDI, SDO, SCK and SS pins as serial
port pins. For the pins to behave as the serial port func-
tion, some must have their data direction bits (in the
TRIS register) appropriately programmed. That is:
• SDI is automatically controlled by the SPI module
• SDO must have TRISC<4> bit cleared
• SCK (Master mode) must have TRISC<6> bit
• SCK (Slave mode) must have TRISC<6> bit set
• SS must have TRISA<5> bit set
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
FIGURE 14-2:
DS41265A-page 170
cleared
Enabling SPI I/O
SPI™ Master SSPM<3:0> = 00xxb
MSb
Serial Input Buffer
Processor 1
Shift Register
SPI™ MASTER/SLAVE CONNECTION
(SSPBUF)
(SSPSR)
LSb
SDO
SCK
SDI
Preliminary
Serial Clock
14.4
Figure 14-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their
programmed clock edge and latched on the opposite
edge of the clock. Both processors should be
programmed to the same Clock Polarity (CKP), then
both controllers would send and receive data at the
same time. Whether the data is meaningful (or dummy
data) depends on the application software. This leads
to three scenarios for data transmission:
• Master sends data – Slave sends dummy data
• Master sends data – Slave sends data
• Master sends dummy data – Slave sends data
SDO
SCK
SDI
Typical Connection
SPI™ Slave SSPM<3:0> = 010xb
MSb
Serial Input Buffer
Shift Register
(SSPBUF)
(SSPSR)
Processor 2
© 2005 Microchip Technology Inc.
LSb