PIC16F946T-I/PT Microchip Technology, PIC16F946T-I/PT Datasheet - Page 22

Microcontroller

PIC16F946T-I/PT

Manufacturer Part Number
PIC16F946T-I/PT
Description
Microcontroller
Manufacturer
Microchip Technology
Series
PIC® 16Fr

Specifications of PIC16F946T-I/PT

Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
336 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA160011 - DAUGHTER BOARD PICDEM LCD 16F91X
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F946T-I/PT
Manufacturer:
MICROCHIP
Quantity:
12 000
Part Number:
PIC16F946T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC16F946
2.2.2.4
The PIE1 register contains the interrupt enable bits, as
shown in Register 2-1.
REGISTER 2-4:
DS41265A-page 20
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PIE1 Register
PIE1 – PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS: 8Ch)
EEIE: EE Write Complete Interrupt Enable bit
1 = Enabled
0 = Disabled
ADIE: A/D Converter Interrupt Enable bit
1 = Enabled
0 = Disabled
RCIE: USART Receive Interrupt Enable bit
1 = Enabled
0 = Disabled
TXIE: USART Transmit Interrupt Enable bit
1 = Enabled
0 = Disabled
SSPIE: Synchronous Serial Port (SSP) Interrupt Enable bit
1 = Enabled
0 = Disabled
CCP1IE: CCP1 Interrupt Enable bit
1 = Enabled
0 = Disabled
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enabled
0 = Disabled
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 7
Legend:
R = Readable bit
- n = Value at POR
R/W-0
EEIE
R/W-0
ADIE
R/W-0
RCIE
Preliminary
W = Writable bit
‘1’ = Bit is set
R/W-0
TXIE
Note:
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SSPIE
R/W-0
Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
CCP1IE
R/W-0
© 2005 Microchip Technology Inc.
x = Bit is unknown
TMR2IE
R/W-0
TMR1IE
R/W-0
bit 0

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