PIC18F2221-E/SS Microchip Technology, PIC18F2221-E/SS Datasheet - Page 224

• Manufacturer Part Number: PIC18F2221-E/SS
• Description: 4KB, Flash, 512bytes-RAM, 25I/O, 8-bit Family,nanoWatt 28 SSOP .209in TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2221-E/SS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

signals from RS-232 to TTL levels also perform an inver-
buffering without inverting the signal.
PIC18F2221/2321/4221/4321 FAMILY
19.2.2
The receiver block diagram is shown in Figure 19-6.
The data is received on the RX pin and drives the data
recovery block. The data recovery block is actually a
high-speed shifter operating at x16 times the baud rate,
whereas the main receive serial shifter operates at the
bit rate or at F
in RS-232 systems.
The RXDTP bit (BAUDCON<5>) allows the RX signal to
be inverted (polarity reversed). Devices that buffer
sion of the signal (when RS-232 = positive, TTL = 0).
Inverting the polarity of the RX pin data by setting the
RXDTP bit allows for the use of circuits that provide
To set up an Asynchronous Reception:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. If any error occurred, clear the error by clearing
11. If using interrupts, ensure that the GIE and PEIE
DS39689F-page 224
Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
Enable the asynchronous serial port by clearing
bit, SYNC, and setting bit, SPEN.
If the signal at the RX pin is to be inverted, set
the RXDTP bit.
If interrupts are desired, set enable bit, RCIE.
If 9-bit reception is desired, set bit, RX9.
Enable the reception by setting bit, CREN.
Flag bit, RCIF, will be set when reception is
complete and an interrupt will be generated if
enable bit, RCIE, was set.
Read the RCSTA register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
enable bit, CREN.
bits in the INTCON register (INTCON<7:6>) are
set.
EUSART ASYNCHRONOUS
RECEIVER
OSC
. This mode would typically be used
19.2.3
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Read RCREG to determine if the device is being
11. If any error occurred, clear the CREN bit.
12. If the device has been addressed, clear the
Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
If the signal at the RX pin is to be inverted, set
the RXDTP bit. If the signal from the TX pin is to
be inverted, set the TXCKP bit.
If interrupts are required, set the RCEN bit and
select the desired priority level with the RCIP bit.
Set the RX9 bit to enable 9-bit reception.
Set the ADDEN bit to enable address detect.
Enable reception by setting the CREN bit.
The RCIF bit will be set when reception is
complete. The interrupt will be Acknowledged if
the RCIE and GIE bits are set.
Read the RCSTA register to determine if any
error occurred during reception, as well as read
bit 9 of data (if applicable).
addressed.
ADDEN bit to allow all received data into the
receive buffer and interrupt the CPU.
SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
© 2009 Microchip Technology Inc.