PIC18F2221-E/SS Microchip Technology, PIC18F2221-E/SS Datasheet - Page 230
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PIC18F2221-E/SS
Manufacturer Part Number
PIC18F2221-E/SS
Description
4KB, Flash, 512bytes-RAM, 25I/O, 8-bit Family,nanoWatt 28 SSOP .209in TUBE
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(402 pages)
2.PIC18F2221-ISO.pdf
(8 pages)
3.PIC18F2221-ISO.pdf
(30 pages)
4.PIC18F2221-ISO.pdf
(46 pages)
Specifications of PIC18F2221-E/SS
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC18F2221-ISO PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
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- PIC18F2221-ISO PDF datasheet #4
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- Download datasheet (7Mb)
PIC18F2221/2321/4221/4321 FAMILY
19.3.2
Once Synchronous mode is selected, reception is
enabled by setting either the Single Receive Enable bit,
SREN (RCSTA<5>), or the Continuous Receive
Enable bit, CREN (RCSTA<4>). Data is sampled on the
RX pin on the falling edge of the clock.
If enable bit SREN is set, only a single word is received.
If enable bit CREN is set, the reception is continuous
until CREN is cleared. If both bits are set, then CREN
takes precedence.
To set up a Synchronous Master Reception:
1.
2.
3.
FIGURE 19-13:
TABLE 19-8:
DS39689F-page 230
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
BAUDCON ABDOVF
SPBRGH
SPBRG
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
Note 1:
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
Name
RC6/TX/CK pin
RC6/TX/CK pin
Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRG16
bit, as required, to achieve the desired baud rate.
Enable the synchronous master serial port by
setting bits, SYNC, SPEN and CSRC.
Ensure bits, CREN and SREN, are clear.
(TXCKP = 0)
(TXCKP = 1)
RC7/RX/DT
(Interrupt)
CREN bit
bit SREN
SREN bit
RCIF bit
RXREG
Write to
These bits are unimplemented on 28-pin devices and read as ‘0’.
Read
EUSART SYNCHRONOUS
MASTER RECEPTION
EUSART Receive Register
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
pin
GIE/GIEH PEIE/GIEL TMR0IE
PSPIF
PSPIE
PSPIP
Q2
CSRC
SPEN
Bit 7
‘0’
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
(1)
(1)
(1)
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
RCIDL
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
bit 0
RXDTP
SREN
TXEN
RCIE
RCIP
RCIF
Bit 5
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
bit 1
TXCKP
INT0IE
CREN
SYNC
Bit 4
TXIF
TXIE
TXIP
bit 2
ADDEN
SENDB
BRG16
SSPIF
SSPIE
SSPIP
bit 3
RBIE
Bit 3
4.
5.
6.
7.
8.
9.
10. Read the 8-bit received data by reading the
11. If any error occurred, clear the error by clearing
12. If using interrupts, ensure that the GIE and PEIE bits
If the signal from the CK pin is to be inverted, set
the TXCKP bit.
If interrupts are desired, set enable bit, RCIE.
If 9-bit reception is desired, set bit, RX9.
If a single reception is required, set bit, SREN.
For continuous reception, set bit, CREN.
Interrupt flag bit, RCIF, will be set when reception
is complete and an interrupt will be generated if
the enable bit, RCIE, was set.
Read the RCSTA register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
RCREG register.
bit, CREN.
in the INTCON register (INTCON<7:6>) are set.
bit 4
TMR0IF
CCP1IF
CCP1IE
CCP1IP
BRGH
FERR
Bit 2
—
bit 5
TMR2IF
TMR2IE
TMR2IP
INT0IF
OERR
TRMT
WUE
Bit 1
bit 6
© 2009 Microchip Technology Inc.
TMR1IE
TMR1IP
TMR1IF
ABDEN
RX9D
TX9D
RBIF
Bit 0
bit 7
Reset Values
Q1 Q2 Q3 Q4
on page
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57
‘0’
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