ADIS16130AMLZ Analog Devices Inc, ADIS16130AMLZ Datasheet - Page 4

• Manufacturer Part Number: ADIS16130AMLZ
• Description: MODULE GYRO RATE SENSOR 24LD
• Manufacturer: Analog Devices Inc

Specifications of ADIS16130AMLZ

• Range °/s: ±250°/s
• Sensitivity: 23,488LSB/°/s
• Typical Bandwidth: 300Hz
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 73mA
• Output Type: Digital
• Operating Temperature: -40°C ~ 85°C
• Package / Case: Module
• No. Of Axes: 1
• Sensor Case Style: ML-24-3
• No. Of Pins: 24
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: -40°C To +85°C
• Msl: MSL 1 - Unlimited
• Acceleration Range: 2000g
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADIS16130
TIMING SPECIFICATIONS
All input signals are specified with 10% to 90% rise and fall times of less than 5 ns.
Table 2.
Parameter
t
Read Operation
Write Operation
1
2
3
1
These numbers are measured with the load circuit shown in Figure 4 and defined as the time required for the output to cross the V
This specification is relevant only if CS goes low while SCLK is low.
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 4. The measured number
is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. Therefore, the times quoted are the true bus relinquish times of the part
and as such are independent of external bus loading capacitances.
t
t
t
t
t
t
t
t
t
t
t
t
t
4
5
5A
6
7
8
9
11
12
13
14
15
16
1
3
1, 2
Min
50
0
0
0
50
50
0
10
0
30
25
50
50
0
Typ
Max
60
60
80
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev. B | Page 4 of 16
Test Conditions/Comments
SYNC pulse width
CS falling edge to SCLK falling edge setup time
SCLK falling edge to data valid delay
DV
CS falling edge to data valid delay
DV
SCLK high pulse width
SCLK low pulse width
CS rising edge after SCLK rising edge hold time
Bus relinquish time after SCLK rising edge
CS falling edge to SCLK falling edge setup
Data valid to SCLK rising edge setup time
Data valid after SCLK rising edge hold time
SCLK high pulse width
SCLK low pulse width
CS rising edge after SCLK rising edge hold time
DD
DD
of 4.75 V to 5.25 V
of 4.75 V to 5.25 V
OL
or V
OH
limits.