EVAL-AD7986EBZ Analog Devices Inc, EVAL-AD7986EBZ Datasheet - Page 17

• Manufacturer Part Number: EVAL-AD7986EBZ
• Description: 18-Bit A/D Converter Eval. Board
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of EVAL-AD7986EBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: ADC
• Kit Application Type: Data Converter
• Silicon Core Number: AD7986
• Kit Contents: Board
• Number Of Adc's: 1
• Number Of Bits: 18
• Sampling Rate (per Second): 2M
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 29mW @ 2MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7986
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DIGITAL INTERFACE
Although the AD7986 has a reduced number of pins, it offers
flexibility in its serial interface modes.
When in CS mode, the AD7986 is compatible with SPI,
MICROWIRE™, QSPI™, and digital hosts. In this mode, the
AD7986 can use either a 3-wire or a 4-wire interface. A 3-wire
interface using the CNV, SCK, and SDO signals minimizes
wiring connections, which is useful, for instance, in isolated
applications. A 4-wire interface using the SDI, CNV, SCK, and
SDO signals allows CNV, which initiates conversions, to be
independent of the readback timing (SDI). This is useful in low
jitter sampling or simultaneous sampling applications.
When in chain mode, the AD7986 provides a daisy-chain feature
using the SDI input for cascading multiple ADCs on a single
data line similar to a shift register. Chain mode is only available
in normal mode (TURBO = low).
The mode in which the part operates depends on the SDI level
when the CNV rising edge occurs. The CS mode is selected if
SDI is high, and the chain mode is selected if SDI is low. The
SDI hold time is such that when SDI and CNV are connected
together, the chain mode is always selected.
In normal mode operation, the AD7986 offers the option of
forcing a start bit in front of the data bits. This start bit can be
used as a busy signal indicator to interrupt the digital host and
trigger the data reading. Otherwise, without a busy indicator,
the user must time out the maximum conversion time prior to
readback.
Rev. B | Page 17 of 28
The busy indicator feature is enabled in CS mode if CNV or
SDI is low when the ADC conversion ends (see Figure 28 and
Figure 32), and TURBO must be kept low for both digital
interfaces.
When CNV is low, reading can occur during conversion and
acquisition, and when split across acquisition and conversion,
as detailed in the following sections.
A discontinuous SCK is recommended because the part is
selected with CNV low, and SCK activity begins to clock
out data.
Note that in the following sections, the timing diagrams
indicate digital activity (SCK, CNV, SDI, and SDO) during
the conversion. However, due to the possibility of performance
degradation, digital activity should occur only prior to the safe
data reading time, t
correction circuitry that can correct for an incorrect bit decision
during this time. From t
and conversion results may be corrupted. Similarly, t
time from the last falling edge of SCK to the rising edge of CNV,
must remain free of digital activity. The user should configure
the AD7986 and initiate the busy indicator (if desired in normal
mode) prior to t
having SCK near the sampling instant. Therefore, it is recom-
mended to keep the digital pins quiet for approximately 20 ns
before and 10 ns after the rising edge of CNV, using a
discontinuous SCK whenever possible to avoid any potential
performance degradation.
DATA
DATA
. It is also possible to corrupt the sample by
DATA
, because the AD7986 provides error
to t
CONV
, there is no error correction,
AD7986
QUIET
, the