EVAL-AD7986EBZ Analog Devices Inc, EVAL-AD7986EBZ Datasheet - Page 24

• Manufacturer Part Number: EVAL-AD7986EBZ
• Description: 18-Bit A/D Converter Eval. Board
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of EVAL-AD7986EBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: ADC
• Kit Application Type: Data Converter
• Silicon Core Number: AD7986
• Kit Contents: Board
• Number Of Adc's: 1
• Number Of Bits: 18
• Sampling Rate (per Second): 2M
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 29mW @ 2MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7986
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7986
CHAIN MODE WITH BUSY INDICATOR
This mode can also be used to daisy-chain multiple AD7986
devices on a 3-wire serial interface while providing a busy
indicator. This feature is useful for reducing component count
and wiring connections, for example, in isolated multiconverter
applications or for systems with a limited interfacing capacity.
Data readback is analogous to clocking a shift register. A
connection diagram example using three AD7986 devices is
shown in Figure 35, and the corresponding timing is given in
Figure 36.
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the busy indicator feature. In this
mode, CNV is held high during the conversion phase and the
ACQUISITION
TURBO = 0
SDO
SDO
CNV = SDI
t
HSCKCNV
SCK
A
B
= SDI
= SDI
SDO
A
B
C
C
CONVERSION
t
DSDOSDI
SDI
t
t
CONV
DSDOSDI
t
t
QUIET
EN
AD7986
CNV
SCK
A
t
t
t
SSDISCK
HSDO
DSDO
1
TURBO
D
D
D
SDO
C
A
B
2
17 D
17 D
17 D
Figure 36. Chain Mode with Busy Indicator Serial Interface Timing
Figure 35. Chain Mode with Busy Indicator Connection Diagram
C
A
B
3
16 D
16 D
16 D
t
SCKH
C
A
B
4
t
SDI
HSDISCK
15
15
15
AD7986
17
t
CNV
SCK
SCK
B
D
D
D
Rev. B | Page 24 of 28
18
C
B
A
1
1
1
TURBO
t
SCKL
SDO
D
D
D
19
C
A
B
0
0
0 D
D
ACQUISITION
20
B
A
17 D
17 D
t
CYC
subsequent data readback. When all ADCs in the chain have
completed their conversions, the SDO pin of the ADC closest to
the digital host (see the AD7986 ADC labeled C in Figure 35) is
driven high. This transition on SDO can be used as a busy indicator
to trigger the data readback controlled by the digital host. The
AD7986 then enters the acquisition phase and powers down.
The data bits stored in the internal shift register are clocked out,
MSB first, by subsequent SCK falling edges. For each ADC, SDI
feeds the input of the internal shift register and is clocked by the
SCK falling edge. Each ADC in the chain outputs its data MSB
first, and 18 × N + 1 clocks are required to read back the N ADCs.
Although the rising edge can be used to capture the data, a digital
host using the SCK falling edge allows a faster reading rate and
consequently more AD7986 devices in the chain, provided that
the digital host has an acceptable hold time.
SDI
21
B
A
t
16
16
ACQ
AD7986
CNV
SCK
35
C
D
D
36
TURBO
B
A
1
1
SDO
D
D
37
B
A
0 D
0
38
A
17
D
CONVERT
DATA IN
CLK
IRQ
39
DIGITAL HOST
A
16
53
t
DSDOSDI
D
54
t
A
DSDOSDI
t
1
DSDOSDI
D
55
A
0