EVAL-AD7986EBZ Analog Devices Inc, EVAL-AD7986EBZ Datasheet - Page 23

• Manufacturer Part Number: EVAL-AD7986EBZ
• Description: 18-Bit A/D Converter Eval. Board
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of EVAL-AD7986EBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: ADC
• Kit Application Type: Data Converter
• Silicon Core Number: AD7986
• Kit Contents: Board
• Number Of Adc's: 1
• Number Of Bits: 18
• Sampling Rate (per Second): 2M
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 29mW @ 2MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7986
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CHAIN MODE WITHOUT BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7986 devices
on a 3-wire serial interface. It is only available in normal conver-
sion mode (TURBO = low). This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7986 devices is
shown in Figure 33, and the corresponding timing is given in
Figure 34.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the busy indicator. In this mode, CNV is
ACQUISITION
TURBO= 0
SDO
SDO
CNV = SDI
t
HSCKCNV
A
B
SCK
= SDI
= SDI
SDO
A
B
C
C
CONVERSION
t
DSDOSDI
t
t
CONV
DSDOSDI
t
t
EN
SSCKCNV
t
t
t
SSDISCK
HSDO
DSDO
1
SDI
D
D
D
C
A
B
2
17 D
Figure 34. Chain Mode Without Busy Indicator Serial Interface Timing
AD7986
17 D
17 D
Figure 33. Chain Mode Without Busy Indicator Connection Diagram
CNV
SCK
A
C
A
B
3
16 D
16 D
16 D
t
TURBO
SCKH
C
B
4
t
A
HSDISCK
15
15
SDO
15
17
t
SCK
D
Rev. B | Page 23 of 28
D
D
18
C
B
A
1
1
1
SDI
t
SCKL
D
D
D
19
C
A
B
0
0 D
0
AD7986
D
CNV
SCK
ACQUISITION
20
B
A
B
17 D
t
17 D
CYC
held high during the conversion phase and the subsequent data
readback. When the conversion is complete, the MSB is output
onto SDO, and the AD7986 enters the acquisition phase and
powers down. The remaining data bits stored in the internal
shift register are clocked by subsequent SCK falling edges. For
each ADC, SDI feeds the input of the internal shift register and
is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 18 × N clocks are required to
read back the N ADCs. The data is valid on both SCK edges.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge allows a faster reading
rate and consequently more AD7986 devices in the chain,
provided that the digital host has an acceptable hold time. The
maximum conversion rate may be reduced due to the total
readback time.
21
B
A
TURBO
t
16
16
ACQ
SDO
35
D
D
36
B
A
1
1
CONVERT
DATA IN
CLK
DIGITAL HOST
D
D
37
B
A
0 D
0
38
A
17
D
39
A
16
53
t
DSDOSDI
D
54
t
DSDOSDI
A
t
1
DSDOSDI
D
55
A
0
AD7986