HW-USB-IIG Xilinx Inc, HW-USB-IIG Datasheet - Page 29

• Manufacturer Part Number: HW-USB-IIG
• Description: IC CABLE
• Manufacturer: Xilinx Inc

Specifications of HW-USB-IIG

• Supply Voltage: 5.25V
• Accessory Type: Platform Cable USB II
• Ic Cable Type: Download Cable
• Connector Type B: USB A Plug
• Connector Type A: 2-mm Shrouded Keyed Socket
• Silicon Family Name: Virtex II, Spartan II
• Core Architecture: FPGA
• Core Sub-architecture: Virtex, Spartan, XC4000
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

X-Ref Target - Figure 30
Interface Pin Descriptions
Table 6: JTAG/SPI/Slave Serial Port: 2-mm Connector Signals
DS593 (v1.2.1) March 17, 2011
Number
Pin
2
4
6
8
speed — degraded
full speed because
12 Mb/s Bus Speed
to slow bus speed
Platform Cable
performance due
1.X Root Hub
Enumerates at
operates at full
root hub only
USB II
Configuration
(A)
500
mA
JTAG
V
TMS
TDO
TCK
REF
Figure 30: Platform Cable USB II Performance with Various Hub Types
12 Mb/s Bus Speed
Programming
1.X Root Hub
Bus-Powered
2.0 External
MODE
speed — degraded
full speed because
Hub
V
Platform Cable
to slow bus speed
performance due
SPI
(B)
Enumerates at
operates at full
REF
–
–
–
root hub only
500
mA
USB II
(1)
< 500
mA
Power
Configuration
Slave-Serial
480 Mb/s Bus Speed
Self-Powered
2.0 Root Hub
V
2.0 External
REF
www.xilinx.com
–
–
–
Enumerates at full speed
performance due to slow
bus speed. Cable may
because 2.0 external
hub operates at full
speed — degraded
Hub
Platform Cable
(C)
not enumerate.
500
mA
USB II
< 500
mA
Direction
Power
Out
Out
In
In
480 Mb/s Bus Speed
Self-Powered
2.0 Root Hub
2.0 External
(2)
Hub
performance due to
Platform Cable
(D)
Hi-Speed — best
high bus speed.
Enumerates at
Target Reference Voltage
should be connected to a voltage bus on the
target system that serves the JTAG, SPI or
Slave Serial interface. For example, when
programming a CoolRunner-II device using
JTAG, V
target V
JTAG Test Mode Select. This pin is the
JTAG mode signal establishing appropriate
TAP state transitions for target ISP devices
sharing the same data stream.
JTAG Test Clock. This pin is the clock
signal for JTAG operations and should be
connected to the TCK pin on all target ISP
devices sharing the same data stream.
JTAG Test Data Out. This pin is the serial
data stream received from the TDO pin on
the last device in a JTAG chain.
500
mA
USB II
500
mA
AUX
REF
bus.
should be connected to the
480 Mb/s Bus Speed
Platform Cable
Description
performance due to
2.0 Root Hub
Hi-Speed — best
high bus speed.
Enumerates at
Platform Cable USB II
USB II
(E)
500
mA
(3)
DS593_30_021408
. This pin
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