HW-USB-IIG Xilinx Inc, HW-USB-IIG Datasheet - Page 8
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HW-USB-IIG
Manufacturer Part Number
HW-USB-IIG
Description
IC CABLE
Manufacturer
Xilinx Inc
Datasheet
1.HW-USB-II-G.pdf
(35 pages)
Specifications of HW-USB-IIG
Supply Voltage
5.25V
Accessory Type
Platform Cable USB II
Ic Cable Type
Download Cable
Connector Type B
USB A Plug
Connector Type A
2-mm Shrouded Keyed Socket
Silicon Family Name
Virtex II, Spartan II
Core Architecture
FPGA
Core Sub-architecture
Virtex, Spartan, XC4000
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
iMPACT 7.1i (and later) provides a feature wherein the BSDL file of each device in a target JTAG chain is scanned to
determine the maximum Boundary-Scan clock (JTAG TCK) frequency. iMPACT 7.1i (and later) automatically restricts the
available TCK_CCLK_SCK selections to frequencies less than or equal to the slowest device in the chain. By default,
iMPACT 7.1i (or later) selects either 6 MHz or the highest common frequency when any device in the JTAG chain is not
capable of 6 MHz operation.
the device data sheet or BSDL file for maximum JTAG TCK specifications.
Note:
Accordingly, users should take care to select a TCK_CCLK_SCK frequency matching the JTAG TCK specifications for the slowest device
in the target chain.
In Slave Serial or Direct SPI Configuration mode, the TCK_CCLK_SCK speed can be set to any one of the available
selections. By default, the TCK_CCLK_SCK speed is set to 6 MHz. Users should take care to select a TCK_CCLK_SCK
frequency matching the Slave Serial clock (CCLK or SPI clock) specification of the target device.
Table 3: Maximum JTAG Clock Frequencies
DS593 (v1.2.1) March 17, 2011
(50, 200 and 400 densities)
(700 and 1400 densities)
Certain Xilinx design tools and iMPACT versions earlier than 7.1i do not restrict the TCK_CCLK_SCK selections in JTAG mode.
XCF00S/XCF00P
Device Family
XC9500/XL/XV
CoolRunner-II
Spartan-3AN
Spartan-3AN
Virtex-II Pro
Spartan-3A
Spartan-3E
Spartan-II
Spartan-3
XC18V00
Spartan
Virtex-II
Virtex-4
Virtex-5
XPLA3
Virtex
Table 3
Maximum JTAG Clock
shows the maximum supported JTAG TCK frequency for a variety of Xilinx devices. See
Frequency (MHz)
10
10
33
10
15
33
33
33
33
33
33
33
33
33
20
30
5
www.xilinx.com
Platform Cable USB II
8