IPR-FIR Altera, IPR-FIR Datasheet - Page 54

• Manufacturer Part Number: IPR-FIR
• Description: IP CORE Renewal Of IP-FIR
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-FIR

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Arria II GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Finite Impulse Response Compiler
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

4–12
Pipelining
FIR Compiler User Guide
1
1
All multicycle variable structures allow the use of hard multipliers in Stratix IV,
Stratix III, Stratix II, Stratix, Cyclone III, and Cyclone II structures. In addition,
Stratix IV, Stratix III, Stratix II, and Stratix multicycle variable implementations take
advantage of the built-in adder structures in the DSP block.
Stratix series devices allow the most flexibility for data and coefficient storage. You
can choose between M512, M4K, and MRAM (when appropriate) for Stratix and
Stratix II devices. Stratix III and Stratix IV devices support MLAB, M9K, and M144K.
Half-Band Decimation Filters
A decimation half-band optimized architecture is available for multicycle variable
structures. This architecture uses half the number of multipliers compared to the
decimation-symmetric architecture when a half-band coefficient set is selected. A
halfband coefficient set has an odd number of symmetric coefficients and every other
coefficient value is 0.
Currently only a single fixed-coefficient set is supported with this optimized
architecture. The data storage and coefficient storage should be set to either Auto or
one of the available block memories. Any value for the decimation factor and the
number of channels can be selected. The number of clocks to compute should be
greater than 1. The FIR Compiler automatically picks the decimation half-band
optimized architecture when these conditions are met.
Symmetric-Interpolation Filters
A new symmetric-interpolation optimized architecture is available for multicycle
variable structures. This architecture requires half the number of multipliers
compared to the standard interpolation filter when a symmetric coefficient set is
selected.
The number of filter taps should be an odd value. Currently only a single fixed-
coefficient set is supported with the optimized architecture. The data storage and
coefficient storage should be set to either Auto or one of the available block
memories. Any value for interpolation factor and number of channels can be selected.
The number of clocks to compute should be greater than 1. The FIR compiler
automatically picks the optimized architecture when these conditions are met.
Pipelining is most effective for producing high-performance filters at the cost of
increased latency: the more pipeline stages you add, the faster the filter becomes.
Pipelining breaks long carry chains into shorter lengths. Therefore, if the carry chains
in your design are already short, adding pipelining may not speed your design.
The FIR Compiler lets you select whether to add one, two, or three pipeline levels.
© December 2010 Altera Corporation
Chapter 4: Functional Description
FIR Compiler