IPR-FIR Altera, IPR-FIR Datasheet - Page 62

• Manufacturer Part Number: IPR-FIR
• Description: IP CORE Renewal Of IP-FIR
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-FIR

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Arria II GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Finite Impulse Response Compiler
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

4–20
Figure 4–17. Single Channel, Single Rate (Serial, Multibit Serial, MCV Multicycle), ast_sink_valid Control
Figure 4–18. Single Channel, Single Rate (Serial, Multibit Serial, MCV Multicycle) ast_sink_ready Control
Interpolation Filter Timing Diagrams
Figure 4–19. Single Channel, Interpolation-by-2 (Parallel, MCV Single Cycle), ast_sink_valid Control
FIR Compiler User Guide
In
ast_sink_valid every three clock cycles.
In
new data in every clock cycle, but the filter accepts new data every three clock cycles
by asserting ast_sink_ready.
In this scenario, a number of data samples are fetched at once and then
ast_sink_ready is de-asserted for a longer period. This behavior is due to the
internal buffering of the Avalon-ST controller.
Figure 4–19
filter with a parallel architecture.
Figure
Figure
4–17, the flow is controlled by the data provider asserting
4–18, ast_sink_valid is always held high and the data provider can feed
and
Figure 4–20 on page 4–21
show a single channel interpolation-by-2
© December 2010 Altera Corporation
Chapter 4: Functional Description
Timing Diagrams