CDB5566 Cirrus Logic Inc, CDB5566 Datasheet
CDB5566
Specifications of CDB5566
CDB-5566
Related parts for CDB5566
CDB5566 Summary of contents
Page 1
kSps, 24-bit ± Features & Description Differential Analog Input On-chip Buffers for High Input Impedance Conversion Time = 200 µS Settles in One Conversion Linearity Error = 0.0005% Signal-to-Noise = 110 dB 24 Bits, ...
Page 2
CHARACTERISTICS AND SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 3
Figure 1. Converter Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 4
CHARACTERISTICS AND SPECIFICATIONS • Min / Max characteristics and specifications are guaranteed over the specified operating conditions. • Typical characteristics and specifications are measured at nominal supply voltages and T • VLR = 0 V. All voltages with respect ...
Page 5
ANALOG CHARACTERISTICS V2- = -2.5 V, ±5%; VL -VLR = 3.3 V, ±5%; VREF = (VREF+) - (VREF-) = 4.096V; MCLK = 8 MHz; SMODE = VL.; BUFEN = V1+ unless otherwise stated. Connected per Parameter Voltage Reference Input Voltage ...
Page 6
SWITCHING CHARACTERISTICS T = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5 VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5% Input levels: Logic ...
Page 7
SWITCHING CHARACTERISTICS T = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5 VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5% Input levels: Logic ...
Page 8
SWITCHING CHARACTERISTICS T = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5 VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5% Input levels: Logic ...
Page 9
SWITCHING CHARACTERISTICS T = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5 VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5% Input levels: Logic ...
Page 10
MCLK RDY CS SCLK( SDO Figure 5. SEC Mode - Discontinuous SCLK Read Timing (Not to Scale) DIGITAL CHARACTERISTICS TMIN to TMAX 3.3V, ± 2.5V, ±5% or 1.8V, ±5%; VLR ...
Page 11
GUARANTEED LOGIC LEVELS T = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5 VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5% Input levels: ...
Page 12
RECOMMENDED OPERATING CONDITIONS ) (VLR = 0V, see Note 17 Parameter Single Analog Supply DC Power Supplies: Dual Analog Supplies DC Power Supplies: Analog Reference Voltage 17. The logic supply can be any value VL – VLR = +1.71 to ...
Page 13
OVERVIEW The CS5566 is a 24-bit analog-to-digital converter capable of 5 kSps conversion rate. The device is ca- pable of switching multiple input channels at a high rate with no loss in throughput. The ADC uses a low-latency digital ...
Page 14
Converter Operation The converter should be reset after the power supplies and voltage reference are stable. The CS5566 converts at 5 kSps when synchronously operated (CONV = VLR) from a 8.0 MHz master clock. Conversion is initiated by taking ...
Page 15
Power Consumption The power consumption of the CS5566 converter is a function of the conversion rate. the typical power consumption of the converter when operating from either MCLK = 8 MHz or MCLK = 4 MHz. The rate at ...
Page 16
Clock The CS5566 can be operated from its internal oscillator or from an external master clock. The state of MCLK determines which clock source will be used. If MCLK is tied low, the internal oscillator will start and be ...
Page 17
Analog Input The analog input of the converter is fully differential with a peak-to-peak input of 4.096 volts on each input. Therefore, the differential, peak-to-peak input is 8.192 volts. This is illustrated in These diagrams also illustrate a differential ...
Page 18
Typical Connection Diagrams The following figure depicts the CS5566 powered from bipolar analog supplies, +2.5 V and - 2 49 47pF +2.048 V 4.99k -2.048 V 4.99k +2.048 -2.048 V 49.9 ...
Page 19
The following figure depicts the CS5566 device powered from a single 5V analog supply. 49.9 2.048 V 47pF 4.548 V 2.5 V 4.99k +0.452 V +4.548 V 2.5 V +0.452 V 49.9 4.096 V 47pF 4.99k +5 V +4.096 Voltage ...
Page 20
AIN & VREF Sampling Structures The CS5566 uses on-chip buffers on the AIN+, AIN-, and the VREF+ inputs. Buffers provide much higher input impedance and therefore reduce the amount of drive current required from an external source. This helps ...
Page 21
Figure 11 through Figure 16 illustrate the performance of the converter with various input signal magni- tudes. 0 277 Hz -20 32k Samples @ 5 kSps -40 -60 -80 -100 -120 -140 -160 -180 0 500 1k Frequency ...
Page 22
Figure 16 illustrates the device with a small signal 1/1,000,000 of full scale. The signal input for figure 15 is about 8.2 microvolts peak to peak, or about 17 codes peak to peak. with a signal at about 2.6 microvolts ...
Page 23
Digital Filter Characteristics The digital filter is designed for fast settling, therefore it exhibits very little in-band attenuation. The filter attenuation is -0.0414 dB at 2.5 kHz when sampling at 5 kSps. Figure 20. Digital Filter Response (DC to ...
Page 24
Serial Port The serial port on the CS5566 can operate in two different modes: synchronous self clock (SSC) mode & synchronous external clock (SEC) mode. The serial port must be placed into the SEC mode if the offset and ...
Page 25
Power Supplies & Grounding The CS5566 can be configured to operate with its analog supply operating from 5V, or with its analog sup- plies operating from ±2.5V. The digital interface supports digital logic operating from either 1.8V, 2.5V, or ...
Page 26
PIN DESCRIPTIONS Chip Select Factory Test Serial Mode Select Differential Analog Input Differential Analog Input Negative Power 1 Positive Power 1 Buffer Enable Voltage Reference Input Voltage Reference Input Bipolar/Unipolar Select Sleep Mode Select CS – Chip Select, Pin ...
Page 27
BP/UP – Bipolar/Unipolar Select, Pin 11 The BP/UP pin determines the span and the output coding of the converter. When set high to select BP (bipolar), the input span of the converter is -4.096 volts to +4.096 volts fully differential ...
Page 28
SCLK – Serial Clock Input/Output, Pin 23 The SMODE pin determines whether the SCLK signal is an input or an output signal. SCLK determines the rate at which data is clocked out of the SDO pin. If the converter is ...
Page 29
PACKAGE DIMENSIONS 24L SSOP PACKAGE DRAWING TOP VIEW INCHES DIM MIN 0.002 A2 0.064 b 0.009 D 0.311 E 0.291 E1 0.197 e 0.022 L 0.025 ∝ 0° Notes: 1.“D” and ...
Page 30
ORDERING INFORMATION Model Linearity CS5566-ISZ 0.0005% 7. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number CS5566-ISZ * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. 8. REVISION HISTORY Revision Date PP1 MAR 2008 Contacting Cirrus Logic Support For all ...